CAT28C256H13I-15 CATALYST SEMICONDUCTOR, CAT28C256H13I-15 Datasheet - Page 7

• Manufacturer Part Number: CAT28C256H13I-15
• Description: IC, EEPROM, 256KBIT, PARALLEL, TSOP-28
• Manufacturer: CATALYST SEMICONDUCTOR

Specifications of CAT28C256H13I-15

• Memory Size: 256Kbit
• Memory Configuration: 32K X 8
• Ic Interface Type: Parallel
• Access Time: 150ns
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: TSOP
• No. Of Pins: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Page Write
extended BYTE WRITE mode) allows from 1 to 64 bytes of
data to be programmed within a single EEPROM write
cycle. This effectively reduces the byte−write time by a
factor of 64.
for t
issuing sequential WE pulses, which load the address and
data bytes into a 64 byte temporary buffer. The page address
where data is to be written, specified by bits A
latched on the last falling edge of WE. Each byte within the
page is defined by address bits A
DATA OUT
ADDRESS
ADDRESS
DATA IN
The page write mode of the CAT28C256 (essentially an
Following an initial WRITE operation (WE pulsed low,
WP
WE
OE
CE
, and then high) the page write mode can begin by
WE
OE
CE
I/O
t
CS
t
AS
0
to A
t
OES
5
(which can be loaded
BYTE 0
Figure 6. Byte Write Cycle [CE Controlled]
t
AH
t
WP
Figure 7. Page Mode Write Cycle
t
6
CW
BYTE 1
to A
http://onsemi.com
t
DS
DATA VALID
14
HIGH−Z
, is
t
BYTE 2
BLC
7
t
OEH
t
CH
in any order) during the first and subsequent write cycles.
Each successive byte load cycle must begin within t
of the rising edge of the preceding WE pulse. There is no
page write window limitation as long as WE is pulsed low
within t
stay high a minimum of t
program cycle to commence. This programming cycle
consists of an erase cycle, which erases any data that existed
in each addressed cell, and a write cycle, which writes new
data back into the cell. A page write will only write data to
the locations that were addressed and will not rewrite the
entire page.
Upon completion of the page write sequence, WE must
BYTE n
BLC MAX
t
BLC
t
DH
.
BYTE n+1
BLC MAX
t
WC
LAST BYTE
BYTE n+2
for the internal automatic
t
WC
BLC MAX