M29F200BT70N6E STMicroelectronics, M29F200BT70N6E Datasheet - Page 5

• Manufacturer Part Number: M29F200BT70N6E
• Description: IC, FLASH, 2MBIT, 70NS, TSOP-48
• Manufacturer: STMicroelectronics

Specifications of M29F200BT70N6E

• Memory Type: Flash - Boot Block
• Memory Size: 2Mbit
• Memory Configuration: 256K X 8 / 128K X 16
• Access Time: 70ns
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: TSOP
• No. Of Pins: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Tables 5 and 6, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V
and Output Enable and keeping Write Enable
High, V
value, see Figure 8, Read Mode AC Waveforms,
and Table 14, Read AC Characteristics, for details
of when the output becomes valid.
Table 5. Bus Operations, BYTE = V
Note: X = V
Table 6. Bus Operations, BYTE = V
Note: X = V
Bus Read
Bus Write
Output Disable
Standby
Read Manufacturer
Code
Read Device Code
Bus Read
Bus Write
Output Disable
Standby
Read Manufacturer
Code
Read Device Code
Operation
Operation
IH
IL
IL
. The Data Inputs/Outputs will output the
or V
or V
IH
IH
.
.
V
V
V
V
V
V
V
V
V
V
E
X
E
X
IH
IH
IL
IL
IL
IL
IL
IL
IL
IL
V
V
V
V
V
V
V
V
V
V
IL
G
G
X
X
IH
IH
IH
IH
IL
IL
IL
IL
IL
IL
, to Chip Enable
IL
IH
V
V
V
V
V
V
V
V
V
V
W
W
X
X
IH
IL
IH
IH
IH
IH
IL
IH
IH
IH
Cell Address
Command Address
X
X
A0 = V
Others V
A0 = V
Others V
Cell Address
Command Address
X
X
A0 = V
Others V
A0 = V
Others V
DQ15A–1, A0-A16
Address Inputs
Address Inputs
IL
IH
IL
IH
, A1 = V
, A1 = V
, A1 = V
, A1 = V
IL
IL
IL
IL
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V
Write operation. See Figures 9 and 10, Write AC
Waveforms, and Tables 15 and 16, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V
A0-A16
or V
or V
or V
or V
IH
IH
IH
IH
IL
IL
IL
IL
IH
, A9 = V
, A9 = V
, A9 = V
, A9 = V
.
ID
ID
ID
ID
,
,
,
,
M29F200BT, M29F200BB
DQ14-DQ8
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ15A–1, DQ14-DQ0
Data Inputs/Outputs
Data Inputs/Outputs
00D4h (M29F200BB)
00D3h (M29F200BT)
IH
, during the whole Bus
Data Output
Data Input
0020h
D4h (M29F200BB)
Hi-Z
Hi-Z
D3h (M29F200BT)
Data Output
Data Input
DQ7-DQ0
Hi-Z
Hi-Z
20h
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