LPC2103FBD48-S NXP Semiconductors, LPC2103FBD48-S Datasheet - Page 16
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LPC2103FBD48-S
Manufacturer Part Number
LPC2103FBD48-S
Description
IC, 32BIT MCU, ARM7, 75MHZ, LQFP-48
Manufacturer
NXP Semiconductors
Datasheet
1.LPC2102FHN48551.pdf
(37 pages)
Specifications of LPC2103FBD48-S
Controller Family/series
(ARM7)
No. Of I/o's
32
Ram Memory Size
8KB
Cpu Speed
70MHz
No. Of Timers
6
Digital Ic Case Style
LQFP
Core Size
32 Bit
Program Memory Size
32KB
Embedded Interface Type
I2C, SPI, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
NXP Semiconductors
LPC2101_02_03_4
Product data sheet
6.14.1 Features
6.15.1 Features
6.14 General purpose 16-bit timers/external event counters
6.15 Watchdog timer
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and optionally generate interrupts or perform other actions at
specified timer values, based on four match registers. It also includes three capture inputs
to trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perform a single capture or match function, providing an
application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.
The LPC2101/02/03 can count external events on one of the capture inputs if the
minimum external pulse is equal or longer than a period of the PCLK. In this configuration,
unused capture lines can be selected as regular timer capture inputs or used as external
interrupts.
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.
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– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
Two 16-bit timer/counters with a programmable 16-bit prescaler.
External event counter or timer operation.
Three 16-bit capture channels that can take a snapshot of the timer value when an
input signal transitions. A capture event may also optionally generate an interrupt.
Four 16-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Four external outputs per timer/counter corresponding to match registers, with the
following capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Rev. 04 — 2 June 2009
Single-chip 16-bit/32-bit microcontrollers
LPC2101/02/03
© NXP B.V. 2009. All rights reserved.
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