PIC24FJ256GA106-I/MR Microchip Technology, PIC24FJ256GA106-I/MR Datasheet - Page 44

• Manufacturer Part Number: PIC24FJ256GA106-I/MR
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-64
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GA106-I/MR

• Controller Family/series: PIC24
• No. Of I/o's: 53
• Ram Memory Size: 16KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Core Size: 16 Bit
• Program Memory Size: 256KB
• Peripherals: ADC, Comparator, PWM, RTC, Timer
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Number Of I /o: 53
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC24FJXXXDA1/DA2/GB2/GA3
5.2.2
When 24-bit instruction words are transferred across
the 16-bit SPI interface, they are packed to conserve
space using the format displayed in
format minimizes traffic over the SPI and provides the
programming executive with data that is properly
aligned for performing table write operations.
FIGURE 5-5:
TABLE 5-1:
DS39970B-page 44
Legend: TBD = To Be Determined
Note 1:
Opcode
LSWx: Least Significant 16 bits of instruction word
15
MSBx: Most Significant Bytes of instruction word
Ch
Dh
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Eh
MSB2
One row of code memory consists of (64) 24-bit words. Refer to
PACKED DATA FORMAT
SCHECK
READC
READP
RESERVED
PROGC
PROGP
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
QVER
RESERVED
PROGW
QBLANK
Mnemonic
PROGRAMMING EXECUTIVE COMMAND SET
PACKED INSTRUCTION
WORD FORMAT
LSW1
LSW2
8 7
(16-bit words)
Length
N/A
N/A
N/A
N/A
N/A
N/A
99
1
3
4
1
4
3
4
5
MSB1
Figure
5-5. This
Time-out
1 ms/row
1 ms
1 ms
5 ms
5 ms
5 ms
1 ms
5 ms
TBD
N/A
N/A
N/A
N/A
N/A
N/A
0
Sanity check.
Read an 8-bit word from the specified Device ID register.
Read N 24-bit instruction words of code memory starting
from the specified address.
This command is reserved; it will return a NACK.
Write an 8-bit word to the specified Device ID registers.
Program one row of code memory at the specified
address, then verify.
This command is reserved; it will return a NACK.
This command is reserved; it will return a NACK.
This command is reserved; it will return a NACK.
This command is reserved; it will return a NACK.
This command is reserved.
Query the programming executive software version.
This command is reserved; it will return a NACK.
Program one instruction word of code memory at the
specified address and then verify.
Query if the code memory is blank.
5.2.3
The
unsupported commands. Additionally, due to the
memory constraints of the programming executive, no
checking is performed on the data contained in the
programmer command. It is the responsibility of the
programmer to command the programming executive
with valid command arguments or the programming
operation may fail. Additional information on error
handling is provided in
Field”.
Note:
programming
When the number of instruction words
transferred is odd, MSB2 is zero and
LSW2 cannot be transmitted.
PROGRAMMING EXECUTIVE
ERROR HANDLING
Table 2-2
(1)
Description
for device-specific information.
executive
 2010 Microchip Technology Inc.
Section 5.3.1.3 “QE_Code
will
“NACK”
all