PIC24FJ64GB004-I/ML Microchip Technology, PIC24FJ64GB004-I/ML Datasheet - Page 2

• Manufacturer Part Number: PIC24FJ64GB004-I/ML
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-44
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB004-I/ML

• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, LIN, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 16 Bit
• Program Memory Size: 64 KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC24FJ64GB004
TABLE 2:
DS80487F-page 2
Output
Compare
Power-
Saving
Modes
USB
USB
UART
Oscillator
SPI
SPI
Triple
(Enhanced)
Comparator
Core
Oscillator
A/D
Interrupts
Oscillator
A/D Converter
Note 1:
Module
Only those issues indicated in the last column apply to the current silicon revision.
SILICON ISSUE SUMMARY
Secondary
Cascaded
mode
Sleep mode
Break
Character
Generation
Oscillator
Configuration
Master mode
Master mode
Doze Mode
Two-Speed
Start-up
INTx
Feature
—
—
—
—
—
—
Number
Item
10.
11.
12.
13.
14.
15.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Cascaded mode does not work as expected.
Issue with Host mode, low-speed operation.
CRC errors while using external transceiver.
Will not generate back-to-back Break characters.
High-current draw when external signal applied under
certain conditions.
wake-up from Sleep (Master mode).
No interrupt generation with internal band gap reference.
Feature is not functional.
External interrupts missed when writing to INTCON2.
POSCEN bit does not work with Primary + PLL modes
Module continues to draw current when disabled.
Transitory increase in I
Spurious transmission and reception of null data on
Inaccurate SPITBF flag with high clock divider.
Instruction execution glitches following Doze bit changes.
Disabled voltage references during Debug mode.
Issue Summary
PD
under certain conditions.
 2010 Microchip Technology Inc.
Revisions
Affected
A2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)