PIC24FJ64GB004-I/ML Microchip Technology, PIC24FJ64GB004-I/ML Datasheet - Page 3

• Manufacturer Part Number: PIC24FJ64GB004-I/ML
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-44
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB004-I/ML

• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, LIN, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 16 Bit
• Program Memory Size: 64 KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Silicon Errata Issues
1. Module: Output Compare (Cascaded
2. Module: Power-Saving Modes (Sleep
 2010 Microchip Technology Inc.
Note:
When using Cascaded (32-bit) mode, Trigger
and Synchronous modes do not work as
expected. The even numbered module does not
become synchronized to the odd numbered
module, resulting in errors in the Most Signifi-
cant 16 bits of the output. In certain modes, the
even numbered module does not generate any
output. This behavior is independent of the
OCTRIG trigger/sync selection for the even
numbered module.
Work around
None.
Affected Silicon Revisions
When entering Sleep mode, a transitory
increase over the specified Power-Down Base
Current (I
observed in some parts and then only under
both of the following circumstances:
• the operating temperature is below -20°C; and
• Sleep mode is entered within 20 seconds of a
Following the increase, I
specified level at 20 seconds after the POR
event.
Deep Sleep mode is not affected.
Work around
None
Affected Silicon Revisions
This issue only applies to devices with date
codes prior to 1001NNN as identified by the
package markings.
A2
A2
X
POR event.
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A2).
PD
Mode)
Mode)
) may occur. This has only been
PD
returns to the normal
3. Module: USB
4. Module: USB
5. Module: UART
While operating in Host mode and attached to a
low-speed device through a full-speed USB hub,
the PRE signal may not be generated correctly.
This will result in not being able to communicate
correctly with the low-speed device.
Work around
Connect low-speed devices directly to the
application and not through a USB hub.
Affected Silicon Revisions
When the module is configured to use an external
transceiver, the CRC5 value of some packets may
be incorrect.
Work around
Use the module’s internal transceiver.
Affected Silicon Revisions
The UART module will not generate consecutive
Break characters. Trying to perform a back-to-
back Break character transmission will cause the
UART module to transmit the dummy character
used to generate the first Break character instead
of transmitting the second Break character. Break
characters are generated correctly if they are
followed by non-Break character transmission.
Work around
None.
Affected Silicon Revisions
A2
A2
A2
X
X
X
PIC24FJ64GB004
DS80487F-page 3