PIC32MX360F256L-80I/BG Microchip Technology, PIC32MX360F256L-80I/BG Datasheet - Page 12
![IC, 32BIT MCU, PIC32, 80MHZ, BGA-100](/photos/12/13/121347/121-xbga_sml.jpg)
PIC32MX360F256L-80I/BG
Manufacturer Part Number
PIC32MX360F256L-80I/BG
Description
IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.MA320002.pdf
(208 pages)
2.DM320001.pdf
(44 pages)
3.PIC32MX320F032H-40IPT.pdf
(48 pages)
4.PIC32MX320F032H-40IPT.pdf
(66 pages)
5.PIC32MX320F032H-40IPT.pdf
(22 pages)
6.PIC32MX320F064H-40IMR.pdf
(172 pages)
Specifications of PIC32MX360F256L-80I/BG
Controller Family/series
PIC32
Ram Memory Size
32KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
No. Of Pwm Channels
5
Core Size
32 Bit
Program Memory Size
256 KB
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
121-TFBGA
Embedded Interface Type
EUSART, I2C, SPI
Rohs Compliant
Yes
Processor Series
PIC32MX3xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
EUART, I2C, SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
85
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARD
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX360F256L-80I/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC32MX3XX/4XX
31. Module: USB
32. Module: USB
33. Module: Prefetch Cache
DS80440D-page 12
The D+ and D– pins are not 5V tolerant. During
normal operation these pins are not subject to 5V.
The 5V tolerance specification is intended to
prevent device damage in an abnormal operation
mode such as connecting a shorted USB cable to
the device.
Work around
Affected Silicon Revisions
The single-ended comparator is detecting SE0
transitions at a higher voltage than indicated in the
USB specification. This is a compliance issue
relating to items ST2 and ST3 in the Peripheral
Silicon checklist, which may result in reduced
noise immunity.
Work around
None.
Affected Silicon Revisions
If the Predictive Prefetch Cache Enable bits
(PREFEN<1:0>) in the CHECON register are non-
zero, improper processor behavior may occur
during a rare boundary condition. This condition
occurs only when predictive prefetch is enabled,
and can occur in both cacheable and non-
cacheable memory areas. The prefetch buffer can
be
instructions causing invalid instruction execution.
This may cause an invalid instruction fault, or
execution of a wrong instruction.
Work around
Make sure that the PREFEN field in CHECON is
programmed to ‘00’. The cache is still used,
although predictive prefetching will be disabled.
Affected Silicon Revisions
Do not subject D+ or D– to 5V.
B2
B2
B2
X
X
X
overwritten
B3
B3
B3
X
X
B4
B4
B4
by
B6
B6
B6
the
“next”
16-bytes
of
34. Module: Flash Program Memory
35. Module: ADC
36. Module: Timers
NVM registers must not be written immediately
after a programming operation is complete. When
a NVM operation completes, the NVMWR bit
(NVMCON<15>) switches states from ‘1’ to ‘0’,
indicating that another NVM operation may be
started. However, there is a period of two internal
FRC clocks after this transition where a write to
NVMCON may not work correctly. Since the
internal FRC clock is 8 MHz, and the system clock
may be much faster, care must be taken to ensure
that the correct delay is met.
Work around
Wait at least 500 ns after seeing a ‘0’ in
NVMCON<15> before writing to any NVM
registers.
Affected Silicon Revisions
When the ADC is in operation, the current channel
is shorted to V
(12 T
impedance sources is that they may not have time
to recover between conversions. The impact on
low-impedance sources is a high current draw,
which may damage either the source or the
device.
Work around
Place a 5k resistor between the device and any
external capacitance on the board to limit current
draw.
Affected Silicon Revisions
Writes to the timer registers PRx and TIMERx
through the Set/Clear/Invert registers corrupts the
data written.
Work around
Do not write to the affected Set/Clear/Invert regis-
ters. Use software read-modify-write sequences to
change individual bits or write directly to the PRx
and TIMERx registers.
Affected Silicon Revisions
B2
B2
B2
X
X
X
AD
) after sampling. The impact on high-
B3
B3
B3
X
B4
B4
B4
X
REF
© 2010 Microchip Technology Inc.
during the conversion period
B6
B6
B6
X