PIC32MX360F256L-80I/BG Microchip Technology, PIC32MX360F256L-80I/BG Datasheet - Page 5
![IC, 32BIT MCU, PIC32, 80MHZ, BGA-100](/photos/12/13/121347/121-xbga_sml.jpg)
PIC32MX360F256L-80I/BG
Manufacturer Part Number
PIC32MX360F256L-80I/BG
Description
IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.MA320002.pdf
(208 pages)
2.DM320001.pdf
(44 pages)
3.PIC32MX320F032H-40IPT.pdf
(48 pages)
4.PIC32MX320F032H-40IPT.pdf
(66 pages)
5.PIC32MX320F032H-40IPT.pdf
(22 pages)
6.PIC32MX320F064H-40IMR.pdf
(172 pages)
Specifications of PIC32MX360F256L-80I/BG
Controller Family/series
PIC32
Ram Memory Size
32KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
No. Of Pwm Channels
5
Core Size
32 Bit
Program Memory Size
256 KB
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
121-TFBGA
Embedded Interface Type
EUSART, I2C, SPI
Rohs Compliant
Yes
Processor Series
PIC32MX3xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
EUART, I2C, SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
85
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARD
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX360F256L-80I/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
TABLE 2:
© 2010 Microchip Technology Inc.
Note 1:
Comparator
Regulator
Oscillator
Oscillator
Module
PORTS
Voltage
RTCC
UART
UART
UART
JTAG
DMA
DMA
DMA
DMA
PMP
PMP
ADC
SPI
SPI
Only those issues indicated in the last column apply to the current silicon revision.
INT0 Interrupt
Overrun Error
Clock Switch
Trigger from
Slave Mode
Slave Mode
Slave Mode
Conversion
SILICON ISSUE SUMMARY (CONTINUED)
Reference
Feature
Receive
Voltage
Status
UART
Buffer
IrDA
BOR
IrDA
—
—
—
—
—
—
—
—
—
®
Number
Item
48.
49.
50.
51.
52.
53.
54.
55.
56.
57.
58.
59.
60.
61.
62.
63.
64.
65.
66.
Clock source switching may cause a general exception or
a POR when switching from a slow clock to a fast clock.
On 64-pin devices, the TMS pin requires an external pull-up. X
Changing the PB divisor on the fly may generate
exceptions.
A suspend followed by an abort does not reset the DMA
pointers.
Turning off DMA during a transfer may have unintended
results.
The PMP interrupt is generated at the start of the PMP
write.
The IBOV overflow flag may not become set when an
overflow occurs.
The channel event bit may be incorrect after a suspend.
DMA events are not detected during a DMA suspend.
Reads of SPIxBUF when SPIRBF is clear will cause
erroneous SPIRBF behavior.
A wake-up interrupt may not be clearable.
TX data is corrupted when BRG values greater than 0x200
are used.
The IrDA minimum bit time is not detected at all baud
rates.
The RTCC alarm registers are reset by any device Reset.
I/O pins do not tri-state immediately if previously driven
high.
The OERR bit does not get cleared on a module Reset.
The OERR bit retains its value even after the UART
module is reinitialized.
The ADC module conversion triggers occur on the rising
edge of the INT0 signal even when INT0 is configured to
generate an interrupt on the falling edge.
The Internal Voltage Reference (IV
(typical) instead of 0.6V as specified in the device data
sheet electrical specifications.
Device may not exit BOR state if BOR event occurs.
Issue Summary
PIC32MX3XX/4XX
REF
) is set to 1.2V
B2 B3 B4 B6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DS80440D-page 5
Revisions
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X