PIC32MX360F256L-80I/BG Microchip Technology, PIC32MX360F256L-80I/BG Datasheet - Page 15
![IC, 32BIT MCU, PIC32, 80MHZ, BGA-100](/photos/12/13/121347/121-xbga_sml.jpg)
PIC32MX360F256L-80I/BG
Manufacturer Part Number
PIC32MX360F256L-80I/BG
Description
IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.MA320002.pdf
(208 pages)
2.DM320001.pdf
(44 pages)
3.PIC32MX320F032H-40IPT.pdf
(48 pages)
4.PIC32MX320F032H-40IPT.pdf
(66 pages)
5.PIC32MX320F032H-40IPT.pdf
(22 pages)
6.PIC32MX320F064H-40IMR.pdf
(172 pages)
Specifications of PIC32MX360F256L-80I/BG
Controller Family/series
PIC32
Ram Memory Size
32KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
No. Of Pwm Channels
5
Core Size
32 Bit
Program Memory Size
256 KB
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
121-TFBGA
Embedded Interface Type
EUSART, I2C, SPI
Rohs Compliant
Yes
Processor Series
PIC32MX3xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
EUART, I2C, SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
85
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARD
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX360F256L-80I/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
51. Module: DMA
52. Module: DMA
53. Module: PMP
54. Module: PMP
© 2010 Microchip Technology Inc.
If a DMA channel is suspend in the middle of a
transfer and an abort is issued, the channel’s
source, destination and cell pointer registers are
not reset.
Work around
Suspend the channel after the channel is aborted.
Affected Silicon Revisions
Turning the DMA module off while a transaction is
in progress may cause invalid instruction or data
fetches.
Work around
Ensure all DMA transactions are complete or abort
DMA transactions before turning off the DMA
module.
Affected Silicon Revisions
In Slave mode, the PMP interrupt is generated at
the start of the PMP write instead of at the end of
the write generated by the master. When the mas-
ter write occurs slowly in relation to the PB clock, it
is possible for the CPU to respond to the interrupt
before the data written by the master has been
latched.
Work around
Poll the PMSTAT register in the ISR to determine
when the data is available.
Affected Silicon Revisions
In Slave mode, the IBOV overflow flag may not
become set when an overflow occurs.
Work around
Do not allow the PMP buffer to overflow.
Affected Silicon Revisions
B2
B2
B2
B2
X
X
X
X
B3
B3
B3
B3
X
X
X
X
B4
B4
B4
B4
X
X
X
X
B6
B6
B6
B6
X
X
X
X
55. Module: DMA
56. Module: DMA
57. Module: SPI
The channel event bit may remain set if a transac-
tion completes as the user suspends the channel
by clearing the corresponding CHEN bit. This has
the effect that as soon as the channel is re-
enabled the event that should have been cleared
after the last transfer will still be pending and the
transfer will begin immediately after the channel is
re-enabled without waiting for an interrupt.
Work around
None.
Affected Silicon Revisions
DMA events are not detected during DMA sus-
pend. Any interrupt event that would initiate a DMA
transfer will not be captured while DMA is sus-
pended. When DMA is re-enabled the event will
have been lost.
Work around
Read the status of the peripheral interrupt flag. If
the interrupt has been asserted, force a DMA
transaction.
Affected Silicon Revisions
Reads of the SPIxBUF register when the SPIRBF
bit is clear will cause erroneous SPIRBF behavior.
Subsequent data in the buffer will not be reflected
by the SPIRBF bit.
Work around
Only read the SPIxBUF register when the SPIRBF
bit is set.
Affected Silicon Revisions
B2
B2
B2
X
X
X
PIC32MX3XX/4XX
B3
B3
B3
X
X
X
B4
B4
B4
X
X
X
B6
B6
B6
X
X
X
DS80440D-page 15