PIC32MX440F128L-80I/BG Microchip Technology, PIC32MX440F128L-80I/BG Datasheet - Page 38

• Manufacturer Part Number: PIC32MX440F128L-80I/BG
• Description: IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F128L-80I/BG

• Controller Family/series: PIC32
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI, USB
• No. Of Pwm Channels: 5
• Core Size: 32 Bit
• Program Memory Size: 128 KB
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Embedded Interface Type: EUSART, I2C, SPI, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EUART, I2C, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARD
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 4-4:
TABLE 4-5:
Legend:
Note
Legend:
Note
BF80_2000 IC1CON
BF80_2010
BF80_2200 IC2CON
BF80_2210
BF80_2400 IC3CON
BF80_2410
BF80_2600 IC4CON
BF80_2610
BF80_2800 IC5CON
BF80_2810
BF80_3000
BF80_3010
BF80_3020
BF80_3200
BF80_3210
Virtual
Virtual
Addr
Addr
SFR
SFR
1:
1:
OC1CON
OC2CON
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor-
mation.
IC1BUF
IC2BUF
IC3BUF
IC4BUF
IC5BUF
OC1RS
Name
Name
OC1R
OC2R
SFR
SFR
(1)
(1)
(1)
(1)
(1)
INPUT CAPTURE1-5 REGISTERS MAP
OUTPUT COMPARE 1-5 REGISTERS MAP
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
31/15
31/15
Bits
Bits
ON
ON
ON
ON
ON
ON
ON
—
—
—
—
—
—
—
30/14
30/14
Bits
Bits
FRZ
FRZ
FRZ
FRZ
FRZ
FRZ
FRZ
—
—
—
—
—
—
—
29/13
29/13
SIDL
SIDL
SIDL
SIDL
SIDL
SIDL
SIDL
Bits
Bits
—
—
—
—
—
—
—
28/12
28/12
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
27/11
27/11
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
26/10
26/10
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ICFEDGE
ICFEDGE
ICFEDGE
ICFEDGE
ICFEDGE
25/9
25/9
Bits
Bits
—
—
—
—
—
—
—
—
—
ICC32
ICC32
ICC32
ICC32
ICC32
Bits
24/8
Bits
24/8
IC1BUF<31:0>
IC2BUF<31:0>
IC3BUF<31:0>
IC4BUF<31:0>
IC5BUF<31:0>
OC1RS<31:0>
—
—
—
—
—
—
—
—
—
OC1R<31:0>
OC2R<31:0>
ICTMR
ICTMR
ICTMR
ICTMR
ICTMR
Bits
23/7
Bits
23/7
—
—
—
—
—
—
—
—
—
Bits
22/6
Bits
22/6
—
—
—
—
—
—
—
—
—
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
OC32
OC32
Bits
21/5
Bits
21/5
—
—
—
—
—
—
—
OCFLT
OCFLT
ICOV
ICOV
ICOV
ICOV
ICOV
20/4
20/4
Bits
Bits
—
—
—
—
—
—
—
OCTSEL
OCTSEL
ICBNE
ICBNE
ICBNE
ICBNE
ICBNE
19/3
19/3
Bits
Bits
—
—
—
—
—
—
—
18/2
18/2
Bits
Bits
—
—
—
—
—
—
—
OCM<2:0>
OCM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
Bits
17/1
Bits
17/1
—
—
—
—
—
—
—
Bits
16/0
Bits
16/0
—
—
—
—
—
—
—