PIC32MX440F128L-80I/BG Microchip Technology, PIC32MX440F128L-80I/BG Datasheet - Page 67
![IC, 32BIT MCU, PIC32, 80MHZ, BGA-100](/photos/12/13/121347/121-xbga_sml.jpg)
PIC32MX440F128L-80I/BG
Manufacturer Part Number
PIC32MX440F128L-80I/BG
Description
IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.MA320002.pdf
(208 pages)
2.DM320001.pdf
(44 pages)
3.PIC32MX320F032H-40IPT.pdf
(48 pages)
4.PIC32MX320F032H-40IPT.pdf
(66 pages)
5.PIC32MX320F032H-40IPT.pdf
(22 pages)
6.PIC32MX320F064H-40IMR.pdf
(172 pages)
Specifications of PIC32MX440F128L-80I/BG
Controller Family/series
PIC32
Ram Memory Size
32KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI, USB
No. Of Pwm Channels
5
Core Size
32 Bit
Program Memory Size
128 KB
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
121-TFBGA
Embedded Interface Type
EUSART, I2C, SPI, USB
Rohs Compliant
Yes
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
EUART, I2C, SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
85
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARD
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX440F128L-80I/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
9.0
Prefetch cache increases performance for applications
executing out of the cacheable program flash memory
regions by implementing instruction caching, constant
data caching, and instruction prefetching.
FIGURE 9-1:
© 2009 Microchip Technology Inc.
Note:
PREFETCH CACHE
CTRL
reference source. Refer to the “PIC32MX
description of this peripheral.
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
Family Reference Manual” Section 4.
“Prefetch Cache” (DS61119) for a detailed
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
Prefetch Ctrl
Cache Ctrl
Miss LRU
Bus Ctrl
Hit LRU
FSM
PREFETCH MODULE BLOCK DIAGRAM
Tag Logic
PreFetch
Pre-Fetch
Hit Logic
Tag
PFM
Preliminary
Address
Encode
Cache
Line
CTRL
9.1
• 16 Fully Associative Lockable Cache Lines
• 16-byte Cache Lines
• Up to 4 Cache Lines Allocated to Data
• 2 Cache Lines with Address Mask to hold
• Pseudo LRU replacement policy
• All Cache Lines are software writable
• 16-byte parallel memory fetch
• Predictive Instruction Prefetch
repeated instructions
Cache Line
PIC32MX3XX/4XX
Pre-Fetch
Features
PreFetch
RDATA
DS61143F-page 65