PIC18F85K22-I/PT Microchip Technology, PIC18F85K22-I/PT Datasheet - Page 51

• Manufacturer Part Number: PIC18F85K22-I/PT
• Description: IC, 8BIT MCU, PIC18F, 64MHZ, TQFP-80
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F85K22-I/PT

• Controller Family/series: PIC18
• No. Of I/o's: 69
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 64MHz
• No. Of Timers: 8
• Core Size: 8 Bit
• Program Memory Size: 32KB
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.5.2
The EC and ECPLL Oscillator modes require an
external clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency,
divided by 4, is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic.
Oscillator mode.
FIGURE 3-5:
An external clock source may also be connected to the
OSC1 pin in HS mode, as shown in
configuration, the divide-by-4 output on OSC2 is not
available. Current consumption in this configuration will
be somewhat higher than EC mode, as the internal
oscillator’s feedback circuitry will be enabled (in EC
mode, the feedback circuit is disabled).
FIGURE 3-6:
3.5.3
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator.
 2009-2011 Microchip Technology Inc.
Clock from
Ext. System
Clock from
Ext. System
Figure 3-5
EXTERNAL CLOCK INPUT
(EC MODES)
PLL FREQUENCY MULTIPLIER
F
OSC
Open
shows the pin connections for the EC
/4
EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
OSC1/CLKI
OSC2/CLKO
OSC1
OSC2
PIC18F87K22
PIC18F87K22
(HS Mode)
Figure
3-6. In this
PIC18F87K22 FAMILY
3.5.3.1
The HSPLL and ECPLL modes provide the ability to
selectively run the device at four times the external
oscillating source to produce frequencies up to
64 MHz.
The PLL is enabled by setting the PLLEN bit
(OSCTUNE<6>) or the PLLCFG bit (CONFIG1H<4>).
The PLLEN bit provides a software control for the PLL,
even if PLLCFG is set to ‘0’. The PLL is enabled only
when the HS or EC oscillator frequency is within the
4 MHz to16 MHz input range.
This enables additional flexibility for controlling the
application’s clock speed in software. The PLLEN
should be enabled in HS or EC Oscillator mode only if
the input frequency is in the range of 4 MHz-16 MHz.
FIGURE 3-7:
3.5.3.2
The PLL is available to the internal oscillator block
when the internal oscillator block is configured as the
primary clock source. In this configuration, the PLL is
enabled in software and generates a clock output of up
to 64 MHz.
The operation of INTOSC with the PLL is described in
Section 3.6.2 “INTPLL
that the PLL is enabled only if the HF-INTOSC
postscaler is configured for 8 MHz or 16 MHz
OSC2
OSC1
HS or EC
PLLCFG (CONFIG1H<4>)
Mode
PLL Enable (OSCTUNE)
HSPLL and ECPLL Modes
PLL and HF-INTOSC
F
F
IN
OUT
PLL BLOCK DIAGRAM
4
Modes”. Care should be taken
Comparator
Loop
Filter
Phase
VCO
DS39960D-page 51
.
SYSCLK