AT80C51RD2-SLSUM Atmel, AT80C51RD2-SLSUM Datasheet - Page 46

• Manufacturer Part Number: AT80C51RD2-SLSUM
• Description: MCU, 8BIT, 8051, 5V, SPI, 20MHZ, 44PLCC
• Manufacturer: Atmel

Specifications of AT80C51RD2-SLSUM

• Controller Family/series: (8051) 8052
• No. Of I/o's: 32
• Ram Memory Size: 1280Byte
• Cpu Speed: 40MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 5
• Core Size: 8bit
• Oscillator Type: External Only
• Processor Series: AT80x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 1280 B
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Cpu Family: AT80
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 40MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 1.25KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

46
AT80C51RD2
Table 12-1.
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-prior-
ity interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of
higher priority level is serviced. If interrupt requests of the same priority level are received simul-
taneously, an internal polling sequence determines which request is serviced. Thus within each
priority level there is a second priority structure determined by the polling sequence.
Table 12-2.
IE0 - Interrupt Enable Register (A8h)
Number
EA
Bit
7
7
6
5
4
3
2
1
0
Priority Level Bit Values
IEO Register
Mnemonic Description
IPH.x
0
0
1
1
ET2
ET1
EX1
ET0
EX0
EC
Bit
EA
EC
ES
6
Enable All interrupt bit
Cleared to disable all interrupts.
Set to enable all interrupts.
PCA interrupt enable bit
Cleared to disable.
Set to enable.
Timer 2 overflow interrupt enable bit
Cleared to disable Timer 2 overflow interrupt.
Set to enable Timer 2 overflow interrupt.
Serial port enable bit
Cleared to disable serial port interrupt.
Set to enable serial port interrupt.
Timer 1 overflow interrupt enable bit
Cleared to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
External interrupt 1 enable bit
Cleared to disable external interrupt 1.
Set to enable external interrupt 1.
Timer 0 overflow interrupt enable bit
Cleared to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
External interrupt 0 enable bit
Cleared to disable external interrupt 0.
Set to enable external interrupt 0.
ET2
5
ES
4
IPL.x
0
1
0
1
ET1
3
EX1
2
Interrupt Level Priority
3 (Highest)
0 (Lowest)
ET0
1
1
2
4113D–8051–01/09
EX0
0