LA-ISPPAC-POWR1014A-01TN48E LATTICE SEMICONDUCTOR, LA-ISPPAC-POWR1014A-01TN48E Datasheet - Page 21

• Manufacturer Part Number: LA-ISPPAC-POWR1014A-01TN48E
• Description: IC, PROG POWER SUPPLY SUPERVISOR TQFP-48
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LA-ISPPAC-POWR1014A-01TN48E

• Input Voltage: 4.5V
• Supply Voltage Range: 2.8V To 3.96
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +105°C
• Frequency: 25MHz
• No. Of Macrocells: 24
• Termination Type: SMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
cuits and ADC. The LA-ispPAC-POWR1014/A can be programmed to operate in three modes: Master mode, Stan-
dalone mode and Slave mode. Table 5 summarizes the operating modes of LA-ispPAC-POWR1014/A.
Table 5. LA-ispPAC-POWR1014/A Operating Modes
A divide-by-32 prescaler divides the internal 8MHz oscillator (or external clock, if selected) down to 250kHz for the
PLD clock and for the programmable timers. This PLD clock may be made available on the PLDCLK pin by closing
SW2. Each of the four timers provides independent timeout intervals ranging from 32µs to 1.96 seconds in 128
steps.
Digital Outputs
The LA-ispPAC-POWR1014/A provides 14 digital outputs, HVOUT[1:2] and OUT[3:14]. Outputs OUT[3:14] are per-
manently configured as open drain to provide a high degree of flexibility when interfacing to logic signals, LEDs,
opto-couplers, and power supply control inputs. The HVOUT[1:2] pins can be configured as either high voltage FET
drivers or open drain outputs. Each of these outputs may be controlled either from the PLD or from the I
ispPAC-POWR1014A only). The determination whether a given output is under PLD or I
a pin-by-pin basis (see Figure 12). For further details on controlling the outputs through I
SMBUS Interface section of this data sheet.
Figure 12. Digital Output Pin Configuration
High-Voltage Outputs
In addition to being usable as digital open-drain outputs, the LA-ispPAC-POWR1014/A’s HVOUT1-HVOUT2 output
pins can be programmed to operate as high-voltage FET drivers. Figure 13 shows the details of the HVOUT gate
drivers. Each of these outputs may be controlled from the PLD, or with the LA-ispPAC-POWR1014A, from the I
bus (see Figure 13). For further details on controlling the outputs through I
section of this data sheet.
Operating Mode
Standalone
Master
Slave
Timer
Closed
Closed
Open
SW0
Closed
Closed
Open
SW1
Digital Control from I
When only one LA-ispPAC-POWR1014/A is used. MCLK pin tristated
When more than one LA-ispPAC-POWR1014/A is
used in a board, one of them should be configured
to operate in this mode.
When more than one LA-ispPAC-POWR1014/As is
used in a board. Other than the master, the rest of
the LA-ispPAC-POWR1014/As should be pro-
grammed as slaves.
(LA-ispPAC-POWR1014A only)
Digital Control
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
from PLD
Condition
21
2
C Register
OUTx
Pin
2
C, please see the I
MCLK pin outputs 8MHz clock
MCLK pin is input
2
C control may be made on
2
C, please see the I
Comments
2
C/SMBUS Interface
2
C bus (LA-
2
2
C/
C