FM6124-QG Ramtron, FM6124-QG Datasheet - Page 40

• Manufacturer Part Number: FM6124-QG
• Description: FRAM, 24KB, EVENT DATA REC, QFP44
• Manufacturer: Ramtron

Specifications of FM6124-QG

• Memory Size: 24KB
• Nvram Features: RTC
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: QFP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Package / Case: QFP
• Interface: I2C
• Memory: RoHS Compliant
• Interface Type: I2C, Serial, 2-Wire
• Rohs Compliant: Yes
• Access Time: 100 KBPs
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Details

}
////////////////////////////////////////////////////////////////////////////////
// Function:
// Description:
// Parameters:
// Return value:
// Remarks:
////////////////////////////////////////////////////////////////////////////////
void
InitI2C()
{
}
Rev. 4.0 (EOL)
July 2010
// Read 5 oldest Events by streaming:
// 1- Move RP to first event:
FM6124WriteReg(EDR_REG_BUFFER_CTRL, EDR_BC_CMD_FIRST);
// 2- Allocate memory for 5 Events
l_puiEvents = malloc(5 * sizeof(struct SEvent));
// 3- Stream 5 Events
if (l_puiEvents != NULL)
{
}
// Final note: to "see" the result of this example, it can be executed with
// Ramtron's Versaware JTAG debugger. At this point, you can verify that all operations
// were completed successfully by looking at the memory content of the Host MCU
// running this program.
if (l_uiDataByte != 0xBD)
{
}
if (l_uiNbEvents != 10)
{
}
return 0;
// Enable I2C module
PERIPHEN1 |= 0x20;
// Init the transmit portion of the I2CRXTX buffer
// I2C Master
I2CCONFIG
I2CIDCFG
// I2C Comm Speed = 96.15 Khz (Max speed of FM6124 is 100kHz)
I2CTIMING
// Make sure FM6124 is responding
while(!IsI2CSlaveReady(I2C_ID_EDR))
{
}
FM6124StreamEventsAtRP(l_puiEvents, 5);
return 1;
return 2;
Delay(1000);
= 0x01;
= 0x41;
= 0x0C;
InitI2C
Enable and initialize I2C in MASTER Mode
None
None
None
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