FM6124 Ramtron Corporation, FM6124 Datasheet
FM6124
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FM6124 Summary of contents
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... Events per second having a minimum duration of 25µs. Other features of the FM6124 include a 16-bit battery backed-up event counter, an early power fail monitoring input, and a user programmable 64-bit serial number. The FM6124 is powered by a 3.0 to 3.6V supply, can function over the industrial temperature range, and is available in a QFP-44 package. QFP-44 P ...
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... Backup supply voltage battery or a large value capacitor backup supply is used, this pin should be tied to VSS and 38 VBAK the VBC bit should be cleared. 39 VDD Supply Supply voltage 40- Leave these pins unconnected Rev. 1.1 Dec. 2007 Function QFP-44 PACKAGE PINOUT FM6124 Event Data Recorder Page ...
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... FUNCTIONAL BLOCKS The functional block diagram of the FM6124 is represented in the figure below. The FM6124 combines the following: • 12 input pins individually configurable for Event recording • Event Buffer memory for event storage implemented as F-RAM • User accessible F-RAM memory • User Accessible Real time clock (RTC) with alarm • ...
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... ACKs (and clocks). When a read operation is complete and no more data is needed, the receiver must NACK the last byte. If the receiver ACKs the last byte, this will cause the FM6124 to attempt to drive the bus on the next clock while the master is sending a new command such as a Stop. ...
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... ACK from the master. If the ACK occurs, the FM6124 will transfer 1 0 the next byte. If the ACK is not sent, the FM6124 will end the read operation. For a write operation, the EMORY FM6124 will accept 8 data bits from the master then send an Acknowledge ...
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... Memory Read Operation There are two types of memory read operations. They are current address read and selective address read current address read, the FM6124 uses the internal address latch to supply the address selective read, the user performs a procedure to first set the address to a specific value. Current Address & ...
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... Slave Address with the LSB set to 1. This indicates that a read operation is requested. After receiving the complete Slave Address, the FM6124 will begin shifting data out from the current register address on the next clock. Auto-increment operates for the special function registers as with the memory address ...
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... R/W bit set to 1 and then send a STOP if the FM6124 fails to respond. At 100 kHz I This delay is correspond to approximately one I This means that if the FM6124 fails to respond to the first read operation, it will respond on the second one. Acknowledge Address Slave Address ...
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... Register Map The FM6124 Event Recorder, RTC, and processor companion functions are accessed via 51 special function registers, which are mapped to unique commands. The interface protocol is described in details in the following pages. The registers contain timekeeping data, alarm settings, control bits, and information flags. A description of each register follows the summary table ...
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EWDF LWDF POR 0x08 10 year 0x07 10 month 0x06 10 date 0x05 0x04 10 hours 0x03 10 minutes 0x02 10 seconds 0x01 CALS 0x00 ~OSCEN AF CF Battery-backed = Nonvolatile = Note: When the device is first powered ...
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... The recorded event data 2 is retrieved through I C mapped registers. The FM6124 is a highly integrated part able to operate in standalone mode and requiring a few external components to operate. Dedicated F-RAM for Event Recording Based on profiles set by the user, Events are recorded in nonvolatile F-RAM memory ...
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... Circular buffer: Initially the Event data will be stored from a base address that we will call FP, for First pointer Rev. 4.0 (EOL) July 2010 and up to the maximum number of Event that the FM6124 have been configured to hold. We will call this address Nmax. Initially the FP pointer is likely lowest possible F- RAM address ...
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... Buffer full at 50% This is done by setting the BF, B75F, B50F bit respectively in the PINEVENTA register For situations where the FM6124 is remote from the host processor always possible for the host processor to retrieve the number of event present in the event buffer by reading the Event buffer counter 16-bit register. ...
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... Retrieving the Number of Unread Events The FM6124 features a 16-bit register that indicate the number of unread event present in the Event Buffer memory. This 16-bit number actually corresponds to the number of events between WP and RP pointers accessible through I C registers addresses 0x2A and 0x2B. ...
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... EDR COMMAND SET The FM6124 responds to commands written to address 2 0x20, through the I C serial port. There are nine unique commands, eight of which are used to retrieve event data, the remaining one is used to set the partition between User Memory and Event Memory. The commands and their effect are listed below ...
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... I2C Start Send I2C EDR (read) Event Data byte Read No Reload Event Data Registers Event Data Register with Next/Previous Event data 0x33 Read? (This operation is automatically performed by the FM6124) Yes Keep Reading Event? I2C Stop End F 19 IGURE ULTIPLE ...
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Since the EDR address register is auto-incrementing unnecessary to send the subsequent address for each byte read from the buffer also unnecessary to begin reading at address 0x2C. In order for the EDR ...
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... The recording of the event data in the F-RAM Event buffer memory require ~100µS per event. simultaneous events occurring on all 12 input of the FM6124, a total 100µS = 1.2ms will be required for the recording of all event Data. During that period of time, event can still be registered, but the Event content will be held into volatile registers ...
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V dropped below started while V is above internally. Table 2 below shows how bits VTP(1:0) control the trip point of the low-V reset. They are located in register DD 18h, bits ...
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... If the power-fail comparator is not used, the PFI pin should be tied to either V drive to V Event Counter The FM6124 offers the user a nonvolatile 16-bit event counter. The input pin CNT has a programmable edge detector. The CNT pin clocks the counter. The counter is located in registers 0E-0Fh. When the programmed edge polarity occurs, the counter will increment its count value ...
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... The typical solution uses a pull-up resistor on the CNT pin and will continuously draw battery current. The FM6124 chip allows the user to invoke a polled mode, which occasionally samples the pin in order to minimize battery drain ...
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When the RTC calibration mode is invoked by setting the CAL bit (register 00h, bit 2), the ACS output pin will be driven with a 512 Hz square wave and the alarm will continue to ...
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... ORE LOCK IAGRAM Calibration When the CAL bit in register 00h is set to a ‘1’, the clock enters calibration mode. The FM6124 devices employ a digital method for calibrating the crystal , the RTC SW oscillator frequency. The digital calibration scheme applies a digital correction to the RTC counters based on the calibration settings, CALS and CAL ...
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... Crystal Type The crystal oscillator is designed to use a 12.5pF crystal without the need for external components, such as loading capacitors. The FM6124 device has built-in loading capacitors that match the crystal 32.768kHz crystal is not used, an external oscillator may be connected to the FM6124. Apply the oscillator to the X1 pin ...
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... FM6124 Event Data Recorder 000000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 ...
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... FM6124 Event Data Recorder 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 ...
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... Contains the Event data seconds in BCD format: Upper quarters contain 10s of seconds Lower Quartet contains unit of seconds Rev. 4.0 (EOL) July 2010 FM6124 Event Data Recorder 2 C registers. Year Month Date Hours Minutes ...
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... Register 2Ah and 2Bh SNAP Write Only: Writing a 1 into the SNAP will perform a snapshot read of all 12 Input of the FM6124 and write the corresponding input logic level into the Register 28h and 29h ...
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... B75F B50F ERR READIR Max number of Events User F-RAM size 4000 0 3000 8 KBytes 2000 16 Kbytes 1000 24 KBytes FM6124 Event Data Recorder ...
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... Hours min.1 10 min.0 Min sec.1 10 sec.0 Seconds VBC F(1:0) Setting 00 (default) 4096 Hz 01 32768 Hz DD FM6124 Event Data Recorder Month.2 Month.1 Month Date.2 Date.1 Date Hours2 Hours.1 Hours Min.2 Min.1 Min Seconds ...
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... July 2010 SN.61 SN.60 SN. SN.53 SN.52 SN. SN.45 SN.44 SN. SN.37 SN.36 SN. SN.29 SN.28 SN. SN.21 SN.20 SN. SN.13 SN.12 SN. SN.5 SN.4 SN EC.13 EC.12 EC. EC.5 EC.4 EC FM6124 Event Data Recorder SN.58 SN.57 SN. SN.50 SN.49 SN. SN.42 SN.41 SN. SN.34 SN.33 SN. SN.26 SN.25 SN. SN.18 SN.17 SN. SN.10 SN.9 SN SN.2 SN.1 SN EC.10 EC.9 EC EC.2 EC.1 EC POLL CP ...
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... WR3 FM6124 Event Data Recorder WDET2 WDET1 WDET0 WDST2 WDST1 WDST0 ...
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... date.1 10 date.0 Date hours.1 10 hours.0 Hours min.1 10 min.0 Min.3 FM6124 Event Data Recorder the POR bit will be set manual reset Year.2 Year.1 Year Month.2 Month.1 Month Date.2 Date ...
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... Reserved bits. Do not use. Should remain set to 0. Rev. 4.0 (EOL) July 2010 sec.1 10 sec.0 Seconds CALS CAL.4 CAL AEN Reserved FM6124 Event Data Recorder Seconds.2 Seconds.1 Seconds CAL.2 CAL.1 CAL CAL W R source power-up after a BAK ...
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Electrical Specifications Absolute Maximum Ratings Symbol V Power Supply Voltage with respect Voltage on any signal pin with respect Backup Supply Voltage BAK T Storage Temperature STG T Lead Temperature (Soldering, 10 ...
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DC Operating Conditions, continued Symbol Parameter V Output Low Voltage @ Output High Voltage OH (PFO Pull-up resistance for RSTB inactive RSTB V Power Fail Input Reference Voltage PFI V ...
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Capacitance (T = 25° C, f=1.0 MHz Symbol Parameter C Input/Output Capacitance IO C X1, X2 Crystal pin Capacitance XTL C Max. Allowable Capacitance on CNT (polled mode) CNT Notes 1 This parameter is characterized but not tested. ...
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... FM6124 Interface Code Example The following C code provides an example of basic interface to the FM6124 using Ramtron’s High Performance VRS51L2070 (8051-based) MCU. //////////////////////////////////////////////////////////////////////////////// // // $Date: 2008-03-10 13:04:43 -0400 (Mon, 10 Mar 2008 $Rev: 250 $ // $Author: smalo $ // $fm6124_basic_example_vrs2070 //////////////////////////////////////////////////////////////////////////////// // // Description: This file contains code examples for a // Host MCU (Ramtron VRS51L2070) communicating with an // Event Data Recorder (Ramtron FM6124 EDR) ...
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... FM6124WriteRTC(&l_oRTCValue); // Configure Event Buffer to 1000 Events FM6124WriteReg(EDR_REG_BUFFER_CTRL, EDR_BC_CMD_EB_SIZE | EDR_BC_VAR_3000_EVENTS); Delay(1); FM6124WriteReg(EDR_REG_BUFFER_CTRL, EDR_BC_CMD_EB_SIZE | EDR_BC_VAR_1000_EVENTS); // Make sure FM6124 has enough time to setup the new Event Buffer (100us required) Delay(1); /////////////////// // F-RAM Write/Read // Write a Byte into the F-RAM at address 0x0000 FM6124WriteFRAM(0x0000, 0xBD); // Read a Byte of Data in the F-RAM at address 0x0000 l_uiDataByte = FM6124ReadFRAM(0x0000) ...
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... InitI2C Enable I2C module PERIPHEN1 |= 0x20; // Init the transmit portion of the I2CRXTX buffer // I2C Master I2CCONFIG = 0x01; I2CIDCFG = 0x41; // I2C Comm Speed = 96.15 Khz (Max speed of FM6124 is 100kHz) I2CTIMING = 0x0C; // Make sure FM6124 is responding while(!IsI2CSlaveReady(I2C_ID_EDR)) { Delay(1000 Rev. 4.0 (EOL) July 2010 ...
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... No ACK received, Slave Module is not ready return RFALSE; } return RTRUE; } //////////////////////////////////////////////////////////////////////////////// // Function: FM6124ReadReg // Description: Read a Register of the FM6124 // Parameters: ruint8 a_uiRegAddr // Return value: ruint8: Value of the register read // Remarks: To Read a register on the I2C, we first need to "fake" write operation in order to send the register address to the // slave module ...
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... READ OPERATION // Dummy Read to clear the I2CRXAVF l_uiValue = I2CRXTX; // Make sure we will ACK the Data we will receive I2CCONFIG &= 0xFD; // Now, send the Read command to the FM6124 I2CRXTX = I2C_ID_EDR | g_uiI2CDevSelect | IC2_READ; // Wait for Data to comeback while(!(I2CSTATUS & 0x02)); l_uiValue = I2CRXTX; ...
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... FM6124WriteRTC(struct SBCDDate *a_poDate) { ruint8 l_uiCounter ruint8 *l_puiDateElement ruint8 l_uiRTCRegValue // First, we need to read the RTC register of the FM6124 l_uiRTCRegValue = FM6124ReadReg(EDR_REG_RTC); // Next, we need to enable the writing of the RTC l_uiRTCRegValue |= 0x02; FM6124WriteReg(EDR_REG_RTC, l_uiRTCRegValue); // Make sure I2C is Idle while(!(I2CSTATUS & 0x08)); // Wait for TX Buffer to be empty while((I2CSTATUS & ...
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... Function: FM6124ReadFRAM // Description: Read 1 byte of Data in the F-RAM of the FM6124 // Parameters: ruint16 a_uiFramAddr // Return value: ruint8: Byte read // Remarks: To Read a data on the I2C, we first need to "fake" write operation in order to send the memory address to the // slave module. //////////////////////////////////////////////////////////////////////////////// ruint8 FM6124ReadFRAM(ruint16 a_uiFramAddr) { ruint8 l_uiDataRead; ...
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... Function: FM6124WriteFRAM // Description: Write 1 byte of Data into the FRAM of the FM6124 // Parameters: ruint16 a_uiFramAddr // ruint8 a_uiValue // Return value: rbool: RTRUE = Operation successful. // Remarks: None //////////////////////////////////////////////////////////////////////////////// rbool FM6124WriteFRAM(ruint16 a_uiFramAddr, ruint8 a_uiValue Make sure I2C is Idle while(!(I2CSTATUS & 0x08)); // Wait for TX Buffer to be empty while((I2CSTATUS & ...
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... RTRUE = Read Ok. // Remarks: None //////////////////////////////////////////////////////////////////////////////// rbool FM6124ReadEventAtRP(struct SEvent *a_poEvent First, we need to indicate the FM6124 that we want to read an Event FM6124WriteReg(EDR_REG_BUFFER_CTRL, EDR_BC_CMD_GET); // Make sure I2C is Idle while(!(I2CSTATUS & 0x08)); // Wait for TX Buffer to be empty while((I2CSTATUS & 0x01) == 0); // Dummy Read, to clear the I2CRxAv flag. ...
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... RFALSE; ruint8* l_puiVufPrt = a_puiEvents; // Send STEAM command to the FM6124 FM6124WriteReg(EDR_REG_BUFFER_CTRL, EDR_BC_CMD_STREAM); // Make sure I2C is Idle while(!(I2CSTATUS & 0x08)); // Wait for TX Buffer to be empty while((I2CSTATUS & 0x01) == 0); // Dummy Read, to clear the I2CRxAv flag. *a_puiEvents = I2CRXTX; ...
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Stop the streaming I2CCONFIG |= 0x02; // Wait for I2C to be Idle and generate a STOP while(!(I2CSTATUS & 0x08)); if ((l_uiCurEvent != a_uiNbEvents) || (l_bEventFF == RTRUE)) { return RFALSE; } return RTRUE; } //////////////////////////////////////////////////////////////////////////////// // Function: ...
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... Mar 2008 $Rev: 249 $ // $Author: smalo $ // $HeadURL: file:…fm6124 //////////////////////////////////////////////////////////////////////////////// // // Description: This file contains C functions declarations and defines // for the Ramtron Event Data Recorder (EDR) FM6124 Remarks Copyright (C) 2008 Ramtron International Corporation // //////////////////////////////////////////////////////////////////////////////// #ifndef FM6124_H #define FM6124_H //////////////////////////////////////////////////////////////////////////////// // Include and defines //////////////////////////////////////////////////////////////////////////////// #include " ...
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... EV_PIN8_FALL = 0x18, EV_PIN8_RISE = 0x19, EV_PIN9_FALL = 0x1A, EV_PIN9_RISE = 0x1B, EV_PIN10_FALL = 0x1C, EV_PIN10_RISE = 0x1D, EV_PIN11_FALL = 0x1E, EV_PIN11_RISE = 0x1F FM6124 Event Data Recorder (EDR) Registers enum EDRRegisters { EDR_REG_RTC = 0x00, EDR_REG_CAL = 0x01, EDR_REG_RTC_SECS = 0x02, EDR_REG_RTC_MINS = 0x03, EDR_REG_RTC_HOURS = 0x04, EDR_REG_RTC_DAY = 0x05, EDR_REG_RTC_DATE = 0x06, EDR_REG_RTC_MONTH = 0x07, ...
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... EDR_BC_CMD_STREAM = 0x3, EDR_BC_CMD_STREAM_KEEP = 0x4, EDR_BC_CMD_SKIP = 0x5, EDR_BC_CMD_FIRST = 0x6, EDR_BC_CMD_LAST = 0x7, EDR_BC_CMD_EB_SIZE = 0x8, EDR_BC_VAR_4000_EVENTS = 0x00, EDR_BC_VAR_3000_EVENTS = 0x40, EDR_BC_VAR_2000_EVENTS = 0x80, EDR_BC_VAR_1000_EVENTS = 0xC0 EDR_REG_PIN_INT_A Bits enum { EDR_PIN_INT_A_BHF_BIT EDR_PIN_INT_A_B75F_BIT EDR_PIN_INT_A_BF_BIT EDR_PIN_INT_A_CLEAR_BIT EDR_PIN_INT_A_CLEAR_BIT_MASK }; #endif // FM6124_H Rev. 4.0 (EOL) July 2010 = 0x10, = 0x20, = 0x40, = 0x80, = 0x7F, Page ...
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... Lead width 0.35 c L/C thickness 0.17 e Lead pitch 0.8 Body edge d1 10º angle d2 Lead angle 6º d3 Lead angle 0º to 7º ORDERING INFORMATION Device Total F-RAM Number Memory Size FM6124-QG 32KB Rev. 4.0 (EOL) July 2010 ...
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Revision History Revision Date 1.0 04/11/2008 4.0 7/20/2010 Rev. 4.0 (EOL) July 2010 Summary Initial release. End of Life. No direct replacement. Page ...