FM21LD16 Ramtron Corporation, FM21LD16 Datasheet

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FM21LD16

Manufacturer Part Number
FM21LD16
Description
2mbit F-ram Memory
Manufacturer
Ramtron Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FM21LD16-60-BG
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
FM21LD16-60-BGTR
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Preliminary
FM21LD16
2Mbit F-RAM Memory
Features
2Mbit Ferroelectric Nonvolatile RAM
SRAM Compatible
Advanced Features
Description
The FM21LD16 is a 128Kx16 nonvolatile memory
that reads and writes like a standard SRAM. A
ferroelectric random access memory or F-RAM is
nonvolatile, which means that data is retained after
power is removed. It provides data retention for over
10 years while eliminating the reliability concerns,
functional
complexities of battery-backed SRAM (BBSRAM).
Fast write timing and high write endurance make the
F-RAM superior to other types of memory.
In-system operation of the FM21LD16 is very similar
to other RAM devices and can be used as a drop-in
replacement for standard SRAM. Read and write
cycles may be triggered by /CE or simply by
changing the address. The F-RAM memory is
nonvolatile due to its unique ferroelectric memory
process. These features make the FM21LD16 ideal
for
frequent or rapid writes in the form of an SRAM.
The FM21LD16 includes a low voltage monitor that
blocks access to the memory array when V
below V
inadvertent access and data corruption under this
condition. The device also features software-
controlled write protection. The memory array is
divided into 8 uniform blocks, each of which can be
individually write protected.
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.0
Dec. 2009
Organized as 128Kx16
Configurable as 256Kx8 Using /UB, /LB
10
NoDelay™ Writes
Page Mode Operation to 40MHz
Advanced High-Reliability Ferroelectric Process
JEDEC 128Kx16 SRAM Pinout
60 ns Access Time, 110 ns Cycle Time
Software Programmable Block Write Protect
nonvolatile
14
DD
Read/Write Cycles
min. The memory is protected against an
disadvantages,
memory applications requiring
and
system
DD
design
drops
Superior to Battery-backed SRAM Modules
Low Power Operation
Industry Standard Configuration
The device is available in a 48-ball FBGA package.
Device specifications are guaranteed over industrial
temperature range –40°C to +85°C.
Pin Configuration
FM21LD16-60-BG
FM21LD16-60-BGTR
No Battery Concerns
Monolithic Reliability
True Surface Mount Solution, No Rework Steps
Superior for Moisture, Shock, and Vibration
2.7V – 3.6V Power Supply
Low Standby Current (90µA typ.)
Low Active Current (8 mA typ.)
Industrial Temperature -40 C to +85 C
48-ball “Green”/RoHS FBGA package
Pin compatible with FM22LD16 (4Mb) and
FM23MLD16 (8Mb)
G
A
B
C
D
E
F
H
1850 Ramtron Drive, Colorado Springs, CO 80921
DQ14
DQ15
DQ8
DQ9
VSS
VDD
Ordering Information
/LB
NC
1
Top View (Ball Down)
DQ10
DQ11
DQ12
DQ13
/OE
/UB
NC
A8
2
Ramtron International Corporation
A14
A12
NC
NC
(800) 545-FRAM, (719) 481-7000
A0
A3
A5
A9
3
60 ns access, 48-ball
“Green”/RoHS FBGA
60 ns access, 48-ball
“Green”/RoHS FBGA,
Tape & Reel
A16
A15
A13
A10
A1
A4
A6
A7
4
http://www.ramtron.com
DQ1
DQ3
DQ4
DQ5
/WE
/CE
A11
A2
5
VDD
DQ0
DQ2
VSS
DQ6
DQ7
NC
NC
6
Page 1 of 14

Related parts for FM21LD16

FM21LD16 Summary of contents

Page 1

... These features make the FM21LD16 ideal for nonvolatile memory applications requiring frequent or rapid writes in the form of an SRAM. The FM21LD16 includes a low voltage monitor that blocks access to the memory array when V below V min. The memory is protected against an DD inadvertent access and data corruption under this condition ...

Page 2

... A(1:0) address inputs allow page mode operation when /CE is low. /WE Input Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the FM21LD16 to write the data on the DQ bus to the F-RAM array. The falling edge of /WE latches a new column address for page mode write cycles. /OE Input Output Enable: When /OE is low, the FM21LD16 drives the data bus when valid read data is available ...

Page 3

... The /UB and /LB pins may be grounded if 1) the system does not perform byte writes and 2) the device is not configured as a 256Kx8. Rev. 1.0 Dec. 2009 A(1:0) Operation X Standby/Idle V Read Change Page Mode Read V Random Read V /CE-Controlled Write 2 V /WE-Controlled Write 3 V Page Mode Write X Starts Precharge FM21LD16 - 128Kx16 FRAM Page ...

Page 4

... In a /CE-controlled write, the /WE signal is asserted prior to beginning the memory cycle. That is, /WE is low when /CE falls. In this case, the device begins the memory cycle as a write. The FM21LD16 will not drive the data bus regardless of the state of /OE as long as /WE is low. Input data must be valid when /CE is deasserted high ...

Page 5

... A flow chart of the entire write protect operation is shown in Figure 2. The write-protect settings are nonvolatile. The factory default: all blocks are unprotected. FM21LD16 - 128Kx16 FRAM 1FFFFh – 1C000h 1BFFFh – 18000h 17FFFh – 14000h 13FFFh – 10000h 0FFFFh – ...

Page 6

... Read 0ECCCh Read 000FFh Read 1FF00h Write 1DAAAh 18h Write 0ECCCh E7h Write 0FF00h Read 00000h Rev. 1.0 Dec. 2009 Figure 2. Write-Protect State Machine - - - - - - ; bits 3 & complement of 18h - ; Data is don’t care - ; return to Normal Operation FM21LD16 - 128Kx16 FRAM Page ...

Page 7

... Software Write Protect Timing SRAM Drop-In Replacement The FM21LD16 has been designed drop-in replacement for standard asynchronous SRAMs. The device does not require /CE to toggle for each new address. /CE may remain low indefinitely. While /CE is low, the device automatically detects address changes and a new access is begun ...

Page 8

... Rev. 1.0 Dec. 2009 SS SS (JEDEC Std JESD22-A114-D) (JEDEC Std JESD22-C101-C) (JEDEC Std JESD22-A115-A) = 2.7V to 3.6V unless otherwise specified) DD Min 2.7 2.2 -0.3 2.4 = -1.0 mA) V -0.2 = -100 2.1 mA) = 100 A) FM21LD16 - 128Kx16 FRAM Ratings -1.0V to +4.5V -1.0V to +4.5V and V < +125 C 260 C TBD TBD TBD MSL-3 Typ Max Units Notes 3.3 3.6 ...

Page 9

... DD Min 110 (to /WE low) 15 (to /WE low 110 3.3V) DD Min - - FM21LD16 - 128Kx16 FRAM Max Units Notes - 110 Max ...

Page 10

... Rev. 1.0 Dec. 2009 = 2.7V to 3.6V unless otherwise specified) DD min. is reached) to First Access Time waveform. power ramp profiles. The behavior of the internal circuits is difficult to predict DD Min 10 Input and Output Timing Levels Output Load Capacitance FM21LD16 - 128Kx16 FRAM Min Max Units Notes 450 - ...

Page 11

... Although sequential column addressing is shown not required. Write Cycle Timing 1 (/WE-Controlled) Write Cycle Timing 2 (/CE-Controlled) CE A(16:0) WE DQ(15:0) UB/LB Rev. 1.0 Dec. 2009 Note: /OE (not shown) is low only to show effect of / pins BLC FM21LD16 - 128Kx16 FRAM Page ...

Page 12

... Write Cycle Timing 3 (/CE low) Note: /OE (not shown) is low only to show effect of / pins Page Mode Write Cycle Timing Although sequential column addressing is shown not required. Power Cycle Timing Rev. 1.0 Dec. 2009 FM21LD16 - 128Kx16 FRAM Page ...

Page 13

... FBGA Package Marking Scheme Legend: RAMTRON XXXXXX= part number, S=speed, P=package XXXXXXX-S-P LLLLLL= lot code, YY=year, WW=work week LLLLLLL YYWW Examples: FM21LD16, 60ns access time, “Green”/RoHS FBGA package, Lot C8556953BG1, Year 2009, Work Week 38 RAMTRON FM21LD16-60-BG C8556953BG1 0938 Rev. 1.0 Dec. 2009 Note: All dimensions in millimeters ...

Page 14

... Revision History Revision Date 1.0 12/22/2009 Rev. 1.0 Dec. 2009 Summary Initial release. FM21LD16 - 128Kx16 FRAM Page ...

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