FM28V010 Ramtron Corporation, FM28V010 Datasheet
FM28V010
Related parts for FM28V010
FM28V010 Summary of contents
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... Superior for moisture, shock, and vibration • Resistant to negative voltage undershoots General Description The FM28V010 is a 16,384 x 8 nonvolatile memory that reads and writes like a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over ...
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... The entire address is latched internally at this point. /WE Input Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the FM28V010 to write the data on the DQ bus to the F-RAM array. The falling edge of /WE latches a new column address for fast page mode write cycles. /OE Input Output Enable: When /OE is low, the FM28V010 drives the data bus when valid data is available ...
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... Read cycle and A(13:3) is latched then. 4) Addresses A(2:0) must remain stable for at least 15 ns during page mode operation. Rev. 1.0 Oct. 2010 A(2:0) Operation X Standby/Idle V Read Change Page Mode Read V Random Read 2 V /CE-Controlled Write /WE-Controlled Write 4 V Page Mode Write X Starts Precharge FM28V010 - 16Kx8 F-RAM Page ...
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... Data polling, a technique used with EEPROMs to determine if a write is complete, is unnecessary. Page Mode Operation The FM28V010 provides the user fast access to any data within a row element. Each row has eight column locations. An access can start anywhere within a row and other column locations may be accessed without the need to toggle the /CE pin ...
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... The device automatically detects an upper order address change which starts a precharge operation, the new address is latched, and Endurance The FM28V010 is capable of being accessed at least 14 10 times – reads or writes. An F-RAM memory operates with a read and restore mechanism. ...
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... SRAM Drop-In Replacement The FM28V010 has been designed drop-in replacement for standard asynchronous SRAMs. The device does not require /CE to toggle for each new address. /CE may remain low indefinitely while V is applied. When /CE is low, the device automatically detects address changes and a new access begins. It also allows page mode operation at speeds up to 33MHz ...
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... Std JESD22-C101-A) (JEDEC Std JESD22-A115-A) = 2.0V to 3.6V unless otherwise specified) DD Min 2.0 0 -0.3 2 mA, V =2.7V -0.2 = -100 µ mA, V =2.7V 150 µA) -0.2V). DD FM28V010 - 16Kx8 F-RAM Ratings -1.0V to +4.5V -1.0V to +4.5V and V < -55°C to +125°C 260° C 2kV 1.25kV 200V MSL-2 Typ Max Units Notes 3.3 3 ...
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... V 2.0 to 2.7V DD Min Max 105 (to /WE low) 20 (to /WE low 105 2.0V to 3.6V unless otherwise specified) DD min) DD waveform. FM28V010 - 16Kx8 F-RAM V 2.7 to 3.6V DD Min Max Units - ...
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... Read Cycle Timing 2 (/CE-controlled) CE A(13:0) OE DQ(7:0) Rev. 1.0 Oct. 2010 ) Min 10 = 3.3V) DD Min - - 1. FM28V010 - 16Kx8 F-RAM Max Units Notes - Years Max Units Notes OHZ Page ...
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... Write Cycle Timing 2 (/CE-Controlled) NOTE: See Write Operation section for detailed description (page 4). Rev. 1.0 Oct. 2010 Note: /OE is low only to show effect of / pins WLC out D in FM28V010 - 16Kx8 F-RAM out Page ...
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... Page Mode Write Cycle Timing Although sequential column addressing is shown not required. Power Cycle Timing Rev. 1.0 Oct. 2010 Note: /OE is low only to show effect of / pins AWH t WLA out FM28V010 - 16Kx8 F-RAM D in Page ...
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... All dimensions in millimeters Pin 1 17.90 ±0.20 1.27 typ 0.33 0.51 SOIC Package Marking Scheme Legend: RAMTRON XXXXXXX-P RYYWWLLLLLLL Example: FM28V010, “Green”/RoHS SOIC package, Rev. 1.0 Oct. 2010 7.50 ±0.10 10.30 ±0.30 2.35 2.65 0.10 0.30 XXXXXX= part number, P= package type (-SG) R=Rev, YY=year, WW=work week, LLLLLL= lot code R=Rev. A, Year 2010, Work Week 21, Lot code 96464473 ...
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... Revision History Revision Date Summary 1.0 10/20/2010 Initial release. Rev. 1.0 Oct. 2010 FM28V010 - 16Kx8 F-RAM Page ...