FM24W64 Ramtron Corporation, FM24W64 Datasheet
FM24W64
Related parts for FM24W64
FM24W64 Summary of contents
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... The FM24W64 provides substantial benefits to users of serial EEPROM, yet these benefits are available in a hardware drop-in replacement. The FM24W64 is available in industry standard 8-pin SOIC package using a familiar two-wire protocol guaranteed over an industrial temperature range of -40°C to +85° ...
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... FM24C64B which protects the upper quadrant only. This pin is pulled down internally. VDD Supply Supply Voltage: 2.7V to 5.5V VSS Supply Ground Rev. 1.0 Nov. 2010 FM24W64 - 64Kb Wide Voltage I2C F-RAM Address Latch Converter Figure 1. Block Diagram 1,024 x 64 FRAM Array 8 Data Latch Page ...
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... This is explained in more detail in the interface section below. Users expect several obvious system benefits from the FM24W64 due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example ...
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... If the receiver acknowledges the last byte, this will cause the FM24W64 to attempt to drive the bus on the next clock while the master is sending a new command such as stop. ...
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... After the address information has been transmitted, data transfer between the bus master and the FM24W64 can begin. For a read operation the FM24W64 will place 8 data bits on the bus then wait for an acknowledge from the master. If the acknowledge occurs, the FM24W64 will transfer the next sequential byte ...
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... FM24W64 should read out the next sequential byte. There are four ways to properly terminate a read operation. Failing to properly terminate the read will most likely create a bus contention as the FM24W64 attempts to read out additional data onto the bus. The four valid methods are: 1. ...
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... Rev. 1.0 Nov. 2010 FM24W64 - 64Kb Wide Voltage I2C F-RAM FM24W64 acknowledges the address, the bus master issues a start condition. This simultaneously aborts the write operation and allows the read command to be issued with the slave address LSB set to a “1”. ...
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... Does not apply to WP, A2-A0 pins. IN OUT The input pull-down circuit is strong (40KΩ) when the input voltage is below V input voltage is above Rev. 1.0 Nov. 2010 FM24W64 - 64Kb Wide Voltage I2C F-RAM Description SS SS (AEC-Q100-002 Rev. E) (AEC-Q100-011 Rev. B) (AEC-Q100-003 Rev. E) =2.7V to 5.5V unless otherwise specified) DD Min 2.7 -0.3 ...
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... Last Access (Stop condition) to Power Down ( Rise Time Fall Time VF DD Notes 1. Slope measured at any point This parameter is characterized and not 100% tested. Rev. 1.0 Nov. 2010 FM24W64 - 64Kb Wide Voltage I2C F-RAM =2.7V to 5.5V unless otherwise specified) DD Min Max Min 0 100 0 4.7 1.3 4.0 0.6 3 4.7 1.3 4.0 0.6 4.7 ...
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... BUF SDA Start Write Bus Timing SCL t SU:STO SDA Start Data Retention Symbol Parameter T +85º +80ºC @ +75ºC @ Rev. 1.0 Nov. 2010 FM24W64 - 64Kb Wide Voltage I2C F-RAM HIGH 1/fSCL t AA Stop Start t HD:DAT t ...
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... XXXXXX= part number, P= package type (G=”Green” SOIC) R=rev code, LLLLLLL= lot code XXXXXXX-P RIC=Ramtron Int’l Corp, YY=year, WW=work week RLLLLLLL RICYYWW Example: FM24W64, “Green”/RoHS SOIC package, Year 2010, Work Week 46 FM24W64-G A00002G1 RIC1046 Rev. 1.0 Nov. 2010 FM24W64 - 64Kb Wide Voltage I2C F-RAM ...
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... Revision History Revision Date 1.0 11/15/2010 Rev. 1.0 Nov. 2010 FM24W64 - 64Kb Wide Voltage I2C F-RAM Summary Initial Release Page ...