FM25640B Ramtron Corporation, FM25640B Datasheet
FM25640B
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FM25640B Summary of contents
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... No write delays are incurred. Data is written to the memory array immediately after it has been successfully transferred to the device. The next bus cycle may commence immediately without the need for data polling. The FM25640B is capable of 12 supporting read/write cycles million times more write cycles than EEPROM ...
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WP Instruction Decode CS Clock Generator Control Logic HOLD Write Protect SCK Instruction Register Address Register Pin Description Pin Name I/O Pin Description /CS Input Chip Select: Enables and disables the device. When /CS is high, the output pin SO ...
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... While there are four such modes, the FM25640B supports modes 0 and 3. Figure 4 shows the required signal relationships for modes 0 and 3. In both cases, data is clocked into the FM25640B on the rising edge of SCK and data is expected on the first rising edge after /CS goes active. If the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge ...
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Figure 2. System Configuration with SPI port Figure 3. System Configuration without SPI port SPI Mode 0: CPOL=0, CPHA=0 7 SPI Mode 3: CPOL=1, CPHA=1 7 Rev. 1.1 Feb. 2011 Figure ...
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... SCK. Command Structure There are six commands called op-codes that can be issued by the bus master to the FM25640B. They are listed in the table below. These op-codes control the functions performed by the memory. They can be divided into three categories. First, there are commands that have no subsequent operations ...
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... Status register. Reading Status provides information about the current state of the write protection features. Following the RDSR op- code, the FM25640B will return one byte with the contents of the Status register. The Status register is described in detail below. Status Register & Write Protection The write protection features of the FM25640B are multi-tiered ...
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... F-RAM technology. EEPROMs, the FM25640B can perform sequential writes at bus speed. No page register is needed and any number of sequential writes may be performed. Write Operation All writes to the memory array begin with a WREN op-code. The next op-code is the WRITE instruction. ...
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... Therefore, endurance cycles are applied for each access: read or write. The F-RAM architecture is based on an array of rows and columns. Each access causes a cycle for an entire row. In the FM25640B, a row is 64 bits wide. Every 8-byte boundary marks the beginning of a new row. Rev. 1.1 Feb. 2011 ...
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Electrical Specifications Absolute Maximum Ratings Symbol Description V Power Supply Voltage with respect Voltage on any pin with respect Storage Temperature STG T Lead Temperature (Soldering, 10 seconds) LEAD V Electrostatic Discharge ...
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AC Parameters (T = -40° 85° Symbol Parameter f SCK Clock Frequency CK t Clock High Time CH t Clock Low Time CL t Chip Select Setup CSU t Chip Select Hold CSH t ...
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Serial Data Bus Timing CS tCSU 1/tCK SCK tH tSU SI SO /Hold Timing CS SCK HOLD SO Power Cycle Timing Power Cycle Timing (T = -40° 85° Symbol t V (min) to First ...
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... Legend: XXXXXXX= part number, P= package type (G=SOIC) R=rev code, LLLLLLL= lot code XXXXXXX-P RIC=Ramtron Int’l Corp, YY=year, WW=work week RLLLLLLL RICYYWW Example: FM25640B, “Green” SOIC package, Year 2010, Work Week 51 FM25640B-G A00002G1 RIC1051 Rev. 1.1 Feb. 2011 Recommended PCB Footprint 3 ...
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Revision History Revision Date 1.0 11/10/2010 1.1 2/15/2011 Rev. 1.1 Feb. 2011 Summary Initial Release Changed t and t spec limits ...