FM25W64 Ramtron Corporation, FM25W64 Datasheet
FM25W64
Related parts for FM25W64
FM25W64 Summary of contents
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... These capabilities make the FM25W64 ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The FM25W64 provides substantial benefits to users of serial EEPROM hardware replacement ...
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WP Instruction Decode CS Clock Generator Control Logic HOLD Write Protect SCK Instruction Register Address Register ` Pin Description Pin Name I/O Pin Description /CS Input Chip Select: Enables and disables the device. When /CS is high, the output pin ...
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... While there are four such modes, the FM25W64 supports modes 0 and 3. Figure 4 shows the required signal relationships for modes 0 and 3. In both cases, data is clocked into the FM25W64 on the rising edge of SCK and data is expected on the first rising edge after /CS goes active. If the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge ...
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Figure 3. 128Kbit (16KB) System Configuration with SPI port Figure 4. System Configuration without SPI port SPI Mode 0: CPOL=0, CPHA=0 7 SPI Mode 3: CPOL=1, CPHA=1 7 Rev. 1.1 Dec. 2010 ...
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... SCK. Command Structure There are six commands called op-codes that can be issued by the bus master to the FM25W64. They are listed in the table below. These op-codes control the functions performed by the memory. They can be divided into three categories. First, there are commands that have no subsequent operations ...
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... Status register. Reading Status provides information about the current state of the write protection features. Following the RDSR op- code, the FM25W64 will return one byte with the contents of the Status register. The Status register is described in detail below. Figure 8. WRSR Bus Configuration (WREN not shown) Status Register & ...
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... F-RAM technology. EEPROMs, the FM25W64 can perform sequential writes at bus speed. No page register is needed and any number of sequential writes may be performed. Write Operation All writes to the memory array begin with a WREN op-code. The next op-code is the WRITE instruction. ...
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... SO Endurance The FM25W64 devices are capable of being accessed 14 at least 10 times, reads or writes. An F-RAM memory operates with a read and restore mechanism. Therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. The F-RAM architecture is based on an array of rows and columns ...
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Electrical Specifications Absolute Maximum Ratings Symbol Description V Power Supply Voltage with respect Voltage on any pin with respect Storage Temperature STG T Lead Temperature (Soldering, 10 seconds) LEAD V Electrostatic Discharge ...
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AC Parameters (T = -40° 85° Symbol Parameter f SCK Clock Frequency C t Clock High Time CH t Clock Low Time CL t Chip Select Setup CSU t Chip Select Hold CSH t ...
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Serial Data Bus Timing /HOLD Timing S C HOLD Q Power Cycle Timing Power Cycle Timing (T = -40° 85° Symbol t V (min) to First Access Start ...
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... XXXXXX= part number, P= package type (G=”Green” SOIC) R=rev code, LLLLLLL= lot code XXXXXXX-P RIC=Ramtron Int’l Corp, YY=year, WW=work week RLLLLLLL RICYYWW Example: FM25W64, “Green” SOIC package, Year 2010, Work Week 46 FM25W64-G A00002G1 RIC1046 Rev. 1.1 Dec. 2010 Recommended PCB Footprint 3 ...
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Revision History Revision Date 1.0 11/15/2010 1.1 12/8/2010 Rev. 1.1 Dec. 2010 Summary Initial Release Fixed endurance section ...