FM23MLD16 Ramtron Corporation, FM23MLD16 Datasheet
FM23MLD16
Available stocks
Related parts for FM23MLD16
FM23MLD16 Summary of contents
Page 1
... The FM23MLD16 F-RAM is available in a 48-ball FBGA surface mount package. Device specifications This is a product that has fixed target specifications but are subject to change pending characterization results. ...
Page 2
... Input Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the FM23MLD16 to write the data on the DQ bus to the F-RAM array. The falling edge of /WE latches a new column address for page mode write cycles. /OE Input Output Enable: When /OE is low, the FM23MLD16 drives the data bus when valid read data is available ...
Page 3
... Read; DQ(7:0) Hi Read; DQ(15:8) Hi Read Write; Mask DQ(7: Write; Mask DQ(15: Write Rev. 1.0 Dec. 2008 FM23MLD16 - 512Kx16 FRAM (multi die) A(18:2) A(1:0) Operation X X Standby/Idle Read Change Change Page Mode Read Change V Random Read V V /CE-Controlled Write ...
Page 4
... Rev. 1.0 Dec. 2008 FM23MLD16 - 512Kx16 FRAM (multi die) Write Operation Writes occur in the FM23MLD16 in the same time interval as reads. The FM23MLD16 supports both /CE- and /WE-controlled write cycles. In both cases, the address A(18:2) is latched on the falling edge of /CE1 (while CE2 high) or the rising edge of CE2 (while /CE1 low) ...
Page 5
... It must remain high for at least the minimum precharge time SRAM Drop-In Replacement The FM23MLD16 has been designed drop-in replacement for standard asynchronous SRAMs. The device does not require the CE pins to toggle for each new address. Both CE pins may remain active indefinitely ...
Page 6
... A simple RC circuit may be inserted in the chip enable path to Rev. 1.0 Dec. 2008 FM23MLD16 - 512Kx16 FRAM (multi die) provide some delay and timing margin for the FM23MLD16’s address setup time general rule, the layout designer may need to add series termination resistors to controller outputs that have fast transitions or routes that are > ...
Page 7
... V = 3.6V, /CE1 CE2 < all memory accesses are blocked regardless of input pin conditions Rev. 1.0 Dec. 2008 FM23MLD16 - 512Kx16 FRAM (multi die (JEDEC Std JESD22-A114-D) (JEDEC Std JESD22-C101-C) (JEDEC Std JESD22-A115-A) = 2.7V to 3.6V unless otherwise specified) DD Min 2.7 2.2 2.2 -0.3 2.4 = -1.0 mA ...
Page 8
... Capacitance ( f=1 MHz Symbol Parameter C Input/Output Capacitance I/O C Input Capacitance (/CE1, CE2, A18) IN1 C Input Capacitance (A17-A0, /WE, /OE, /LB, /UB) IN2 Rev. 1.0 Dec. 2008 FM23MLD16 - 512Kx16 FRAM (multi die) = 2.7V to 3.6V unless otherwise specified) DD Min 115 - - 2.7V to 3.6V unless otherwise specified) ...
Page 9
... Input Pulse Levels Input Rise and Fall Times 3 ns Read Cycle Timing 1 (/CE1 low, CE2 high, /OE low) Read Cycle Timing 2 (/CE-controlled) Rev. 1.0 Dec. 2008 FM23MLD16 - 512Kx16 FRAM (multi die) = 2.7V to 3.6V unless otherwise specified) DD min waveform. power ramp profiles. The behavior of the internal circuits is difficult to predict ...
Page 10
... Page Mode Read Cycle Timing 1. Although sequential column addressing is shown not required. Write Cycle Timing 1 (/WE-Controlled, /OE low) CE1 CE2 t AS A(18:0) WE DQ(15:0) Write Cycle Timing 2 (/CE-Controlled) Rev. 1.0 Dec. 2008 FM23MLD16 - 512Kx16 FRAM (multi die WLC ...
Page 11
... Write Cycle Timing 3 (/CE1 low, CE2 high) Page Mode Write Cycle Timing 1. Although sequential column addressing is shown not required. Rev. 1.0 Dec. 2008 FM23MLD16 - 512Kx16 FRAM (multi die) Page ...
Page 12
... LLLLLL= lot code, YY=year, WW=work week LLLLLLL YYWW Examples: FM23MLD16, “Green”/RoHS FBGA package, Lot C8556953BG1, Year 2008, Work Week 44 RAMTRON FM23MLD16-60-BG C8556953BG1 0844 Rev. 1.0 Dec. 2008 FM23MLD16 - 512Kx16 FRAM (multi die 0.75 typ 8.00 BSC 0.40±0.05 6.00 BSC 0.25 Note: All dimensions in millimeters. Bottom View 4 3 ...
Page 13
... Revision History Revision Date 1.0 12/12/2008 Rev. 1.0 Dec. 2008 FM23MLD16 - 512Kx16 FRAM (multi die) Summary Initial release. Page ...