fm3808 Ramtron Corporation, fm3808 Datasheet
fm3808
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fm3808 Summary of contents
Page 1
... Tracks Seconds through Centuries in BCD Format Tracks Leap Years through 2099 Runs from a 32.768 kHz Timekeeping Crystal Description The FM3808 combines a 256Kb FRAM array with a real-time clock and a system supervisor function. An external 32.768 kHz crystal drives the timekeeping function. It maintains time and date settings in the absence of system power through the use of a backup battery power source ...
Page 2
... Supply Ground. SS Rev. 1.3 (EOL) Feb. 2006 Switched power Watchdog timebase Address Decoder/ Clock/Calendar 16 Clock/Calendar Figure 1. Block Diagram is drawn from V when V BAK BAK FM3808 FRAM Array 32,752x8 Data Address Bus Interface Registers is supplied by a BAK is below the V voltage. DD BAK Page ...
Page 3
... Overview The FM3808 integrates three complementary but distinct functions under a common interface in a single package. First, is the 32Kx8 FRAM memory block (minus 16 bytes), second is the real-time clock/calendar, and third is the system supervisor. The functions are integrated to enhance their individual performance, so that each provides better capability than three similar stand-alone devices ...
Page 4
... hours.1 10 hours.0 Hours.3 Hours2 min.1 10 min.0 Min sec.1 10 sec.0 Seconds.3 Seconds Reserved CALS CAL.3 FM3808 Year.2 Year.1 Year Month.1 Month Date.2 Date.1 Date Day.2 Day.1 Day Hours.1 Hours.0 ...
Page 5
... D3 WDT.5 WDT.4 WDT PFE ABE H date.1 10 date.0 Date hours.1 10 hours.0 Hours min.1 10 min.0 Min.3 FM3808 WDT.2 WDT.1 WDT P/L Reserved Reserved Date.2 Date.1 Date Hours2 Hours.1 Hours Min.2 Min.1 Min.0 ...
Page 6
... FFh to any of the timekeeping registers. Updates to the timekeeping core occur continuously except when frozen. A diagram of the timekeeping core is shown in Figure 2. Backup Power The real-time clock/calendar permanently powered operation. When primary FM3808 Seconds.1 Seconds ...
Page 7
... Power monitor & band-gap (V Flags connected to related functions All FRAM access & updates Calibration operation INT pin if programmed as active-high Oscillator 32.768 kHz crystal Date Hours 6 bits 6 bits Days 3 bits User Interface Registers FM3808 < < 2.0V 512 Hz W Clock Update Divider Logic ...
Page 8
... Therefore, the correction will not appear on the 512 Hz output. The calibration correction must be applied using the values shown in Table 2. The timekeeping accuracy can be verified by comparing the FM3808 time to a reference source. FM3808 calibration However, the ...
Page 9
... Program Calibration D4-D0 0 4.34 4.35 13.02 13.03 21.70 21.71 30.38 30.39 39.06 39.07 47.74 47.75 56.42 56.43 65.10 65.11 73.78 73.79 82.46 82.47 91.14 91.15 99.82 99.83 108.50 108.51 117.18 117.19 125.86 125.87 134.54 FM3808 00000b 10001b 10010b 10011b 10100b 10101b 10110b 10111b 11000b 11001b 11010b 11011b 11100b 11101b 11110b 11111b 00000b 00001b 00010b 00011b 00100b 00101b 00110b 00111b 01000b 01001b 01010b 01011b 01100b 01101b 01110b 01111b ...
Page 10
... The interrupt function is described below. Alarm condition No match required = alarm 1/second Alarm when seconds match, = alarm 1/minute Alarm when seconds, minutes match, = alarm 1/hour Alarm when seconds, minutes, hours match, = alarm 1/day Alarm when seconds, minutes, hours, date match, = alarm 1/month FM3808 Page ...
Page 11
... Flags/Control register is read by the user. The user can also enable an optional interrupt source to drive the INT pin if the watchdog timeout occurs. The interrupt function is described on page 13. Clock 1 Hz Divider 32 Hz Zero Counter Compare Load Register 7FF7.5-0 Watchdog register FM3808 7FF0.7 WDF Page ...
Page 12
... Power Monitor The FM3808 provides a power management scheme with either power-fail interrupt or processor-reset capability. It also controls the internal switch to backup power for the timekeeper and protects the memory from low-V access. The power monitor is DD based on an internal band-gap reference circuit that compares the V voltage to various thresholds ...
Page 13
... The control bits are summarized as follows. Watchdog Interrupt Enable - WIE. When set to 1, the watchdog timer drives the INT pin as well as an internal flag when a watchdog timeout occurs. When FM3808 VDD INT Page ...
Page 14
... I than 1 A. This will reduce the expected life of the battery since I If the FM3808 is stored for days/weeks with battery attached and the clock/calendar values are not important, you should disable the RTC oscillator by setting the /OSCEN bit ...
Page 15
... In a /CE controlled write, the /WE signal is asserted prior to beginning the memory cycle. That is, /WE is low when /CE falls. In this case, the part begins the memory cycle as a write. The FM3808 will not drive the data bus regardless of the state of /OE /WE controlled write, the memory cycle begins on the falling edge of /CE ...
Page 16
... Block 2 0800h 0800h 07FFh 07FFh Block 1 Block 1 0400h 0400h 03FFh 03FFh Block 0 Block 0 0000h 0000h Figure 6. Address Blocks A9-A8 11b 10b 01b 00b A0-A7 00h 01h 02h 03h FCh FDh FEh Figure 7. Row and Column Organization FM3808 Block 4 A14-A10 00100b FFh Page ...
Page 17
... The reason for /CE to strobe for each address is two- fold: it latches the new address and creates the necessary precharge period while /CE is high. CE Address 1 Address 2 Data 1 Invalid Memory Signaling Relationship CE Address 1 Data 1 FM3808 An example of the signal Data 2 Address 2 Data 2 Page ...
Page 18
... Crystal Selection The second passive component needed for the RTC function is the timekeeping crystal. A 32.768 kHz time-base is required, and the FM3808 is designed to accept a low cost crystal. The major parameters associated with the crystal are timekeeping accuracy and backup current. The FM3808 is designed to accept a crystal with a characteristic capacitance ...
Page 19
... DD Min 4.5 2.5 4.35 4.2 V BAK 1.2 2.0 -0.5 = -2.0mA) 2.4 = 4.2mA) < BAK . V is also the point at which the timekeeper draws current from the V BAK SW = 0.4V. OL < FM3808 Ratings -1.0V to +7.0V -1.0V to +7.0V and V < V +1. - 125 C 300 C Typ Max Units Notes 5.0 5 500 2 A 150 3 A 3.0 ...
Page 20
... Slew rate for proper transition between the locked-out condition and normal operation. Rev. 1.3 (EOL) Feb. 2006 = 4.5V to 5.5V unless otherwise specified 4.5V to 5.5V unless otherwise specified) DD Parameter FM3808 Min Max Units Notes 2,000 ns 130 ...
Page 21
... Rev. 1.3 (EOL) Feb. 2006 = 4.5V to 5.5V unless otherwise specified) DD Min 150 - Min Units 10 Years = 5V) DD Max Units Equivalent AC Load Circuit 1.5V Output FM3808 Typ Max Units Notes 200 300 ms 1 100 ns 2 Notes Notes 1.3V 3300 50 pF Page ...
Page 22
... Timing Diagrams CE A0-14 OE DQ0-7 CE A0- DQ0-7 Rev. 1.3 (EOL) Feb. 2006 Read Cycle Timing /CE-Controlled Write Cycle Timing FM3808 OHZ Page ...
Page 23
... CE A0- DQ0-7 out DQ0-7 in Rev. 1.3 (EOL) Feb. 2006 /WE-Controlled Write Cycle Timing FM3808 Page ...
Page 24
... RST INT Inputs CE INT source occurs INT CE Rev. 1.3 (EOL) Feb. 2006 Power Cycle Timing INT INT t PD INT Pin Timing INT source occurs P/L=1 t IPU FM3808 INT RST t FCO t IPU t RI P/L=0 t FCO INT source flag cleared Page ...
Page 25
... DD BAK INT pin Timing at Power Up V BAK New value written (register is battery backed) driven low t IPU (~ 200 ms) , however the timing diagram above illustrates BAK (max). BAK FM3808 (max BAK is DD (max). When V power is applied IPU is established, the register 7FF6h ...
Page 26
... Mechanical Drawing 32-pin Shrunk TSOP-I (8.0 x 13.4 mm) All dimensions in millimeters 7.90-8.10 13.30-13.55 0.50-0.70 Rev. 1.3 (EOL) Feb. 2006 13.30-13.55 11.70-11.90 R 0.08 min R 0.08-0. FM3808 1.20 max 0.50 typ 0.17-0.27 typ 0.95-1.05 0.05-0.15 Page ...
Page 27
... Removed all references to the use of a capacitor as a backup source. Added Recommended Power-Up Sequence section. Changed Mechanical Drawing title. Not Recommended for New Designs. End of Life. No Direct Replacement. Alternate solution is FM1808 with FM4005. Last time buy is Sept. 2006. FM3808 to 5ns. DH Page ...