fm3808 Ramtron Corporation, fm3808 Datasheet - Page 17

• Manufacturer Part Number: fm3808
• Description: 256kb Bytewide Fram W/ Real-time Clock
• Manufacturer: Ramtron Corporation

FRAM Design Considerations
SRAM and FRAM alike begin each read/write cycle
with a new address being driven prior to the chip
enable transition low. The falling edge of chip enable
latches the address and a memory access starts. For
subsequent memory accesses, SRAMs allow /CE to
remain low while the address bus changes. FRAM
devices do not allow this signalling. Every FRAM
access requires a falling edge of /CE, therefore users
cannot ground this pin as you might with SRAM.
Users who are modifying existing designs to use
FRAM should examine the memory controller for
timing compatibility of address and control pins.
Rev. 1.3 (EOL)
Feb. 2006
signaling
signaling
SRAM
FRAM
Figure 8. Memory Address and /CE Relationships
Address
Address
Valid Memory Signaling Relationship
Data
Data
Invalid Memory Signaling Relationship
CE
CE
Address 1
Address 1
Data 1
Each memory access must be qualified with a low
transition of /CE. In many cases, this is the only
change
relationships is shown in Figure 8 below. Also shown
is a common SRAM signal relationship that will not
work for the FRAM devices.
The reason for /CE to strobe for each address is two-
fold: it latches the new address and creates the
necessary precharge period while /CE is high.
Data 1
Address 2
required.
Address 2
An example
Data 2
Data 2
of the signal
Page 17 of 27
FM3808