fm3808 Ramtron Corporation, fm3808 Datasheet - Page 13

• Manufacturer Part Number: fm3808
• Description: 256kb Bytewide Fram W/ Real-time Clock
• Manufacturer: Ramtron Corporation

Interrupts
The supervisor was designed to serve diverse
applications. Its sophistication and programmability
make the supervisor function highly configurable for
the host system. The interrupt block is capable of
providing system interrupt or reset conditions, and
can even power up a system at a preprogrammed
time. Although the INT pin is described as an
interrupt, the pin may be used as a reset source as
well.
The supervisor provides three potential interrupt
sources. They include the watchdog timer, the power
monitor, and the clock/calendar alarm. Each can be
individually enabled and assigned to drive the INT
pin. In addition, each has an associated flag bit that
the host processor can use to determine the cause of
the interrupt.
Some of the sources have additional control bits that
determine functional behavior. In addition, the pin
driver has three bits that specify its behavior when an
According to the programming selections, the pin can
be driven in the backup mode for an alarm interrupt.
In addition, the pin can be an active low (open-drain)
or active high (push-pull) driver. If programmed for
operation during backup mode, it can only be active
low. Lastly, the pin can provide a one-shot function
so that the active condition is a pulse, or a level
condition. In One-Shot mode, the pulse width is
internally fixed at approximately 200 ms. This mode
is intended to reset a host microcontroller. In Level
Rev. 1.3 (EOL)
Feb. 2006
Watchdog
Monitor
VINT
Power
Alarm
Timer
Clock
ABE
AIE
AF
WDF
WIE
PFE
PF
Figure 5. Interrupt Block Diagram
interrupt occurs. A functional diagram of the interrupt
logic is shown below.
The three interrupts each have a source and an
enable. Both the source and the enable must be active
(true high) in order to generate an interrupt output.
Only one source is necessary to drive the pin. The
user can identify the source by reading the
Flags/Control register, which contains the flags
associated with each source. All flags are cleared to 0
when the register is read. The cycle must be a
complete read cycle (/WE high), otherwise the flags
will not be cleared. The power monitor has two
programmable settings that are explained above in the
power monitor section.
Once an interrupt source is active, the pin driver
determines the behavior of the output. It has two
programmable settings as shown below. Pin driver
control bits are located in the Interrupts register
7FF6h bits D3-D2.
mode, the pin goes to its active polarity until the
Flags/Control register is read by the user. This mode
is intended to be used as an interrupt to a host
microcontroller. The control bits are summarized as
follows.
Watchdog Interrupt Enable - WIE. When set to 1, the
watchdog timer drives the INT pin as well as an
internal flag when a watchdog timeout occurs. When
Driver
H/L
P/L
Pin
VDD
INT
Page 13 of 27
FM3808