fm3808 Ramtron Corporation, fm3808 Datasheet - Page 11

• Manufacturer Part Number: fm3808
• Description: 256kb Bytewide Fram W/ Real-time Clock
• Manufacturer: Ramtron Corporation

Watchdog Timer
The Watchdog timer is a free running down counter
that uses the 32 Hz clock (31.25 ms) derived from the
crystal oscillator. The oscillator must be running
(/OSCEN=0) for the watchdog to function. It begins
counting down from the value loaded in the
Watchdog Timer register (7FF7h).
The counter consists of a loadable register and a free
running counter. On power up, the watchdog timeout
value in 7FF7h is loaded into the counter load
register. Counting begins on power up and restarts
from the loadable value any time the Watchdog
Strobe WDS bit (7FF7h bit D7) is set to 1. The
counter is compared to terminal value of 0. If the
counter reaches this value, it causes an internal flag
and an optional interrupt output (see interrupts
below). The user can prevent the timeout interrupt by
setting WDS bit to 1 prior to the counter reaching 0.
This causes the counter to be reloaded with the
watchdog timeout value and to be restarted. As long
as the user sets the WDS bit prior to the counter
reaching the terminal value, the interrupt and flag
never occurs.
Rev. 1.3 (EOL)
Feb. 2006
WDW
WDS
Oscillator
Watchdog
register
write to
D
32.768 kHz
Q
Q
Figure 3. Watchdog Timer Block Diagram
Load Register
Watchdog
Counter
register
Divider
Clock
32 Hz
7FF7.5-0
New timeout values can be written by setting the
watchdog write bit (7FF7h bit D6) to 0. When the
/WDW bit is 0 (from a previous operation), new
writes to the watchdog timeout value 7FF7h bits D5-
D0 allow the timeout value to be modified. When
/WDW is a 1, then writes to bits 7FF7h bits D4-D0
will be ignored. The /WDW function allows a user to
set the WDS bit without concern that the watchdog
timer value will be modified. A logical diagram of the
watchdog timer is shown below. Note that setting the
watchdog timeout value to 0 would be otherwise
meaningless and therefore disables the watchdog
function.
The output of the watchdog timer is a flag bit WDF
(7FF0h bit D7) that is set if the watchdog is allowed
to timeout. The flag is set upon a watchdog timeout
and cleared when the Flags/Control register is read by
the user. The user can also enable an optional
interrupt source to drive the INT pin if the watchdog
timeout occurs. The interrupt function is described on
page 13.
1 Hz
Compare
Zero
WDF
7FF0.7
Page 11 of 27
FM3808