fm3808 Ramtron Corporation, fm3808 Datasheet - Page 14

• Manufacturer Part Number: fm3808
• Description: 256kb Bytewide Fram W/ Real-time Clock
• Manufacturer: Ramtron Corporation

WIE is set to 0, the watchdog timer affects only the
internal flag.
Alarm Interrupt Enable – AIE. When set to 1, the
alarm match drives the INT pin as well as an internal
flag. When set to 0, the alarm match only affects the
internal flag.
Power-fail Interrupt Enable - PFE. When set to 1, the
power-fail monitor drives the pin as well as an
internal flag. When set to 0, the power-fail monitor
affects only the internal flag.
Alarm Battery-backup Enable - ABE. When set to 1,
the clock alarm interrupt (as controlled by AIE) will
function even in battery backup mode. When set to 0,
the alarm will occur only when V
should only be set when the INT pin is programmed
for active low operation. In addition, it only functions
with the clock alarm, not the watchdog. If enabled,
the power monitor will drive the interrupt during all
normal V
application for ABE is intended for power control,
where a system powers up at a predetermined time.
Depending on the application, it may require
dedicating the INT pin to this function.
High/Low – H/L. When set to a 1, the INT pin is
active high and the driver mode is push-pull. The INT
pin can drive high only when V
0, the INT pin is active low and the driver mode is
open-drain. Active low (open drain) is operational
even in battery backup mode.
Pulse/Level – P/L. When set to a 1 and an interrupt
occurs, the INT pin is driven for approximately 200
ms. When P/L is set to a 0, the INT pin is driven high
or low (determined by H/L) until the Flags/Control
register is read.
When an enabled interrupt source activates the INT
pin, an external host can read the Flags/Control
register to determine the cause. Remember that all
flags will be cleared when the register is read. If the
INT pin is programmed for Level mode, then the
Rev. 1.3 (EOL)
Feb. 2006
DD
conditions regardless of the ABE bit. The
DD
>V
LO
DD
. When set to a
> V
LO
. AIE
condition will clear and the INT pin will return to its
inactive state. If the pin is programmed for Pulse
mode, then reading the flag also will clear the flag
and the pin. The pulse will not complete its specified
duration if the Flags/Control register is read. If the
INT pin is used as a host reset, then the Flags/Control
register cannot be read during a reset. Care should be
taken in reading the flags as a new source may occur
after the pin goes active but before the register is
read.
During a power-on reset with no battery, the
interrupt register is automatically loaded with the
value 24h. This causes power-fail interrupt to be
enabled with an active-low pulse. See INT Timing
at Power Up diagram on page 25.
Recommended Power-Up Sequence
The FM3808 registers must be programmed in order
for the device to operate properly. The chip also
must be power sequenced properly. The following is
the recommended sequence:
The V
RTC oscillator is enabled (running) and RTC/Alarm
set. Interrupt enable bits may be set as desired.
CAUTION: If V
battery, there is no guarantee that I
than 1 A. This will reduce the expected life of the
battery since I
If the FM3808 is stored for days/weeks with battery
attached and the clock/calendar values are not
important, you should disable the RTC oscillator by
setting the /OSCEN bit to a 1.
1.
2.
3.
4.
5.
DD
Apply V
Apply V
Remove V
Apply V
Program registers via 2-wire interface
power supply may be removed once the
BAK
BAK
DD
DD
could be much greater than 1 A.
DD
DD
(while V
(while V
power is applied without a
BAK
BAK
is still applied)
is still applied)
BAK
will be less
Page 14 of 27
FM3808