FM24CL64B Ramtron Corporation, FM24CL64B Datasheet
FM24CL64B
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FM24CL64B Summary of contents
Page 1
... No write delays are incurred. Data is written to the memory array in the cycle after it has been successfully transferred to the device. The next bus cycle may commence immediately without the need for data polling. The FM24CL64B is capable of 14 supporting 10 read/write cycles million times more write cycles than EEPROM ...
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... Write Protect. When WP is high, addresses in the entire memory map will be write- protected. When WP is low, all addresses may be written. This pin is pulled down internally. VDD Supply Supply Voltage: 2.7V to 3.6V VSS Supply Ground Rev. 1.2 Feb. 2011 Address Latch Converter Figure 1. FM24CL64B Block Diagram FM24CL64B 1,024 x 64 FRAM Array 8 Data Latch Page ...
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... This is explained in more detail in the interface section below. Users expect several obvious system benefits from the FM24CL64B due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example ...
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... Slave Address The first byte that the FM24CL64B expects after a start condition is the slave address. As shown in Figure 4, the slave address contains the device type, the device select address bits, and a bit that specifies if the transaction is a read or a write ...
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... After the address information has been transmitted, data transfer between the bus master and the FM24CL64B can begin. For a read operation the FM24CL64B will place 8 data bits on the bus then wait for an acknowledge from the master. If the acknowledge occurs, the FM24CL64B will transfer the next sequential byte ...
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... Read Operation There are two basic types of read operations. They are current address read and selective address read current address read, the FM24CL64B uses the internal address latch to supply the address selective read, the user performs a procedure to set the address to a specific value. ...
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... Acknowledge Data Figure 7. Current Address Read Acknowledge 1 A Data Byte A Acknowledge Data Figure 8. Sequential Read Address Start A Address LSB A S Acknowledge Figure 9. Selective (Random) Read FM24CL64B No Acknowledge Stop Acknowledge Stop Data Byte Acknowledge Address Slave Address 1 A Data Byte 1 P ...
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... Rev. E) =2.7V to 3.65V unless otherwise specified) DD Min 2.7 -0 other inputs -0.3V Stop command issued FM24CL64B Ratings -1.0V to +5.0V -1.0V to +5.0V and V < V +1. -55°C to +125°C 260° C 4kV 1.25kV 300V MSL-1 Typ Max Units Notes 3.3 3.65 V 100 µ ...
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... DD Max Units Notes 2.7V to 3.65V unless otherwise specified) DD min) DD waveform. DD FM24CL64B Min Max Units Notes 400 0 1000 kHz 1 0.6 µs 0.4 µs 0.9 0.55 µs 0.5 µs 0.25 µs 0.25 µ 100 ns 300 300 ns 2 300 100 ns 2 0.25 µs ...
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... 0 HIGH 1/fSCL t AA Stop Start t HD:DAT t t SU:DAT HD:STA Stop Start Min FM24CL64B Equivalent AC Load Circuit 3.6V 1100 Ω Output 100 LOW SP t HD:DAT t SU:DAT t DH Acknowledge t AA Acknowledge Max Units Notes - Years - ...
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... Legend: XXXXXX= part number, P= package type (G=SOIC) R=rev code, LLLLLLL= lot code XXXXXXXP RIC=Ramtron Int’l Corp, YY=year, WW=work week RLLLLLLL RICYYWW Example: FM24CL64B, “Green” SOIC package, Year 2010, Work Week 47 FM24CL64BG A00002G1 RIC1047 Rev. 1.2 Feb. 2011 FM24CL64B Page ...
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... Legend: R=Ramtron, G=”green” TDFN package, XXXX=base part number LLLL= lot code, RGXXXX YY=year, WW=work week LLLL YYWW Example: “Green” TDFN package, FM24CL64B, Lot 0003, Industrial temperature, Year 2011, Work Week 07 R4L64B 0003 1107 Rev. 1.2 Feb. 2011 Exposed metal pad. ...
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... Revision History Revision Date 1.0 11/10/2010 1.1 12/20/2010 1.2 2/15/2011 Rev. 1.2 Feb. 2011 Summary Initial Release Added 4x4.5mm DFN package. Added ESD ratings. Updated DFN package marking. Changed t spec limits. FM24CL64B and Page ...