FM6124-QG Ramtron, FM6124-QG Datasheet - Page 6

• Manufacturer Part Number: FM6124-QG
• Description: FRAM, 24KB, EVENT DATA REC, QFP44
• Manufacturer: Ramtron

Specifications of FM6124-QG

• Memory Size: 24KB
• Nvram Features: RTC
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: QFP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Package / Case: QFP
• Interface: I2C
• Memory: RoHS Compliant
• Interface Type: I2C, Serial, 2-Wire
• Rohs Compliant: Yes
• Access Time: 100 KBPs
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Details

Memory Read Operation
There are two types of memory read operations. They
are current address read and selective address read. In
a current address read, the FM6124 uses the internal
address latch to supply the address. In a selective
read, the user performs a procedure to first set the
address to a specific value.
Current Address & Sequential Read
As mentioned above the FM6124 uses an internal
latch to supply the address for a read operation. A
current address read uses the existing value in the
address latch as a starting place for the read
operation. The system reads from the address
immediately following that of the last operation.
To perform a current address read, the bus master
supplies a slave address with the LSB set to 1. This
indicates that a read operation is requested. After
receiving the complete device address, the FM6124
will begin shifting data out from the current address
on the next clock. The current address is the value
held in the internal address latch.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte the internal address counter
will be incremented.
Rev. 1.1
Dec. 2007
By FM6124
By FM6124
By Master
By Master
Start
S
Start
S
Slave Address
Slave Address
0
A
Address & Data
Address MSB
0
F
F
IGURE
A
IGURE
6.
Address & Data
5. S
Acknowledge
Address MSB
MULTIPLE
INGLE
A
B
Address LSB
B
YTE
Acknowledge
YTE
M
There are four ways to terminate a read operation.
Failing to properly terminate the read will most likely
create a bus contention as the FM6124 attempts to
read out additional data onto the bus. The four valid
methods follow.
1.
2.
3.
4.
If the internal address reaches the top of memory, it
will wrap around to 0000h on the next read cycle.
The figures below show the proper operation for
current address reads.
Selective (Random) Read
There is a simple technique that allows a user to
select a random address location as the starting point
for a read operation. This involves using the first
three bytes of a write operation to set the internal
address followed by subsequent read operations.
M
A
EMORY WRITE
Each time the bus master acknowledges a byte,
this indicates that the FM6124 should read out
the next sequential byte.
EMORY WRITE
The bus master issues a NACK in the 9
cycle and a Stop in the 10
illustrated in the diagrams below and is
preferred.
The bus master issues a NACK in the 9
cycle and a Start in the 10
The bus master issues a Stop in the 9
cycle.
The bus master issues a Start in the 9
cycle.
Address LSB
A
Data Byte
FM6124 Event Data Recorder
A
A
th
.
th
Data Byte
clock cycle. This is
Data Byte
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th
th
th
th
A
clock
clock
clock
clock
A
Stop
Stop
P
P