DSPIC30F4012-20E/SP Microchip Technology, DSPIC30F4012-20E/SP Datasheet - Page 104
![IC,DSP,16-BIT,CMOS,DIP,28PIN,PLASTIC](/photos/6/59/65908/150-28-dip_sml.jpg)
DSPIC30F4012-20E/SP
Manufacturer Part Number
DSPIC30F4012-20E/SP
Description
IC,DSP,16-BIT,CMOS,DIP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F4012-30ISO.pdf
(238 pages)
3.DSPIC30F4012-30ISO.pdf
(18 pages)
4.DSPIC30F4012-30ISO.pdf
(6 pages)
5.DSPIC30F4012-30ISO.pdf
(16 pages)
6.DSPIC30F4012-30ISO.pdf
(22 pages)
Specifications of DSPIC30F4012-20E/SP
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
DSPIC30F401220ESP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F4012-20E/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F4012-30ISO PDF datasheet #2
- DSPIC30F4012-30ISO PDF datasheet #3
- DSPIC30F4012-30ISO PDF datasheet #4
- DSPIC30F4012-30ISO PDF datasheet #5
- DSPIC30F4012-30ISO PDF datasheet #6
- Current page: 104 of 238
- Download datasheet (4Mb)
dsPIC30F4011/4012
15.8
An Independent PWM Output mode is required for
driving certain types of loads. A particular PWM output
pair is in the Independent Output mode when the
corresponding PTMODx bit in the PWMCON1 register
is set. No dead-time control is implemented between
adjacent PWM I/O pins when the module is operating
in the Independent Output mode and both I/O pins are
allowed to be active simultaneously.
In the Independent Output mode, each duty cycle
generator is connected to both of the PWM I/O pins in
an output pair. By using the associated duty cycle reg-
ister and the appropriate bits in the OVDCON register,
the user may select the following signal output options
for each PWM I/O pin operating in the Independent
Output mode:
• I/O pin outputs PWM signal
• I/O pin inactive
• I/O pin active
15.9
The PWM module produces single pulse outputs when
the PTCON control bits, PTMOD<1:0> = 10. Only
edge-aligned outputs may be produced in the Single
Pulse mode. In Single Pulse mode, the PWM I/O pin(s)
are driven to the active state when the PTEN bit is set.
When a match with a duty cycle register occurs, the
PWM I/O pin is driven to the inactive state. When a
match with the PTPER register occurs, the PTMR reg-
ister is cleared, all active PWM I/O pins are driven to
the inactive state, the PTEN bit is cleared and an
interrupt is generated.
DS70135G-page 104
Independent PWM Output
Single Pulse PWM Operation
15.10 PWM Output Override
The PWM output override bits allow the user to manu-
ally drive the PWM I/O pins to specified logic states,
independent of the duty cycle comparison units.
All control bits associated with the PWM output over-
ride function are contained in the OVDCON register.
The upper half of the OVDCON register contains six
bits, POVDxH<3:1> and POVDxL<3:1>, that determine
which PWM I/O pins will be overridden. The lower half
of
POUTxH<3:1> and POUTxL<3:1>, that determine the
state of the PWM I/O pins when a particular output is
overridden via the POVD bits.
15.10.1
When a PWMxL pin is driven active via the OVDCON
register, the output signal is forced to be the comple-
ment of the corresponding PWMxH pin in the pair.
Dead-time insertion is still performed when PWM
channels are overridden manually.
15.10.2
If the OSYNC bit in the PWMCON2 register is set, all
output overrides performed via the OVDCON register
are synchronized to the PWM time base. Synchronous
output overrides occur at the following times:
• Edge-Aligned mode when PTMR is zero.
• Center-Aligned modes when PTMR is zero and
when the value of PTMR matches PTPER.
the
OVDCON
COMPLEMENTARY OUTPUT MODE
OVERRIDE SYNCHRONIZATION
register
© 2010 Microchip Technology Inc.
contains
six
bits,
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