DSPIC30F6013-20E/PF Microchip Technology, DSPIC30F6013-20E/PF Datasheet - Page 135
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
DSPIC30F6013-20E/PF
Manufacturer Part Number
DSPIC30F6013-20E/PF
Description
IC,DSP,16-BIT,CMOS,TQFP,80PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F6014-20IPF.pdf
(228 pages)
2.DSPIC30F6014-20IPF.pdf
(22 pages)
3.DSPIC30F6014-20IPF.pdf
(28 pages)
Specifications of DSPIC30F6013-20E/PF
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
132KB (44K x 24)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1AC164314 - MODULE SKT FOR PM3 80PFAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F601320EPF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6013-20E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
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The 20-bit mode treats each 256-bit AC-Link frame as
sixteen, 16-bit time slots. In the 20-bit AC-Link mode,
the module operates as if COFSG<3:0> = 1111 and
WS<3:0> = 1111. The data alignment for 20-bit data
slots is ignored. For example, an entire AC-Link data
frame can be transmitted and received in a packed
fashion by setting all bits in the TSCON and RSCON
SFRs. Since the total available buffer length is 64 bits,
it would take 4 consecutive interrupts to transfer the
AC-Link frame. The application software must keep
track of the current AC-Link frame segment.
18.7
The DCI module is configured for I
a value of ‘01’ to the COFSM<1:0> control bits in the
DCICON1 SFR. When operating in the I
DCI module will generate frame synchronization sig-
nals with a 50% duty cycle. Each edge of the frame
synchronization signal marks the boundary of a new
data word transfer.
The user must also select the frame length and data
word size using the COFSG and WS control bits in the
DCICON2 SFR.
© 2006 Microchip Technology Inc.
I
2
S Mode Operation
2
S mode by writing
dsPIC30F6011/6012/6013/6014
2
S mode, the
18.7.1
The WS and COFSG control bits are set to produce the
period for one half of an I
frame length is the total number of CSCK cycles
required for a left or a right data word transfer.
The BLEN bits must be set for the desired buffer length.
Setting BLEN<1:0> = 01 will produce a CPU interrupt,
once per I
18.7.2
As per the I
default, begin one CSCK cycle after a transition of the
WS signal. A ‘MS bit left justified’ option can be
selected using the DJST control bit in the DCICON2
SFR.
If DJST = 1, the I
tified. The MSb of the data word will be presented on
the CSDO pin during the same CSCK cycle as the ris-
ing or falling edge of the COFS signal. The CSDO pin
is tri-stated after the data word has been sent.
2
S frame.
2
I
LENGTH SELECTION
I
S specification, a data word transfer will, by
2
2
S FRAME AND DATA WORD
S DATA JUSTIFICATION
2
S data transfers will be MSb left jus-
2
S data frame. That is, the
DS70117F-page 133
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