PIC16F630-E/SL Microchip Technology, PIC16F630-E/SL Datasheet - Page 31

• Manufacturer Part Number: PIC16F630-E/SL
• Description: 14 PIN, 1.75KB STD FLASH, 64 RAM, 12 I/O,
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F630-E/SL

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.0
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 4-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
4.1
Timer mode is selected by clearing the T0CS bit
(OPTION_REG<5>). In Timer mode, the Timer0
module will increment every instruction cycle (without
prescaler). If TMR0 is written, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
FIGURE 4-1:
 2010 Microchip Technology Inc.
T0CKI
Note:
pin
(= F
CLKOUT
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
OSC
T0SE
TIMER0 MODULE
Timer0 Operation
Additional information on the Timer0
module is available in the PIC
Reference Manual, (DS33023).
/4)
Watchdog
WDTE
Timer
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
T0CS
0
1
PSA
0
1
®
Mid-Range
Prescaler
8-bit
8
PS0 - PS2
Counter mode is selected by setting the T0CS bit
(OPTION_REG<5>). In this mode, the Timer0 module
will increment either on every rising or falling edge of
pin RA2/T0CKI. The incrementing edge is determined
by
(OPTION_REG<4>). Clearing the T0SE bit selects the
rising edge.
4.2
A Timer0 interrupt is generated when the TMR0
register timer/counter overflows from FFh to 00h. This
overflow sets the T0IF bit. The interrupt can be masked
by
(INTCON<2>) must be cleared in software by the
Timer0 module Interrupt Service Routine before re-
enabling this interrupt. The Timer0 interrupt cannot
wake the processor from Sleep since the timer is shut-
off during Sleep.
Note:
clearing the T0IE bit (INTCON<5>). The T0IF bit
the
Timer0 Interrupt
Counter mode has specific external clock
requirements. Additional information on
these requirements is available in the PIC
Mid-Range
(DS33023).
PSA
PSA
source
1
0
1
0
PIC16F630/676
SYNC 2
Cycles
Time-out
edge
WDT
Reference
(T0SE)
Data Bus
Set Flag bit T0IF
8
DS40039F-page 31
TMR0
on Overflow
control
Manual,
bit
®