PIC16F630-E/SL Microchip Technology, PIC16F630-E/SL Datasheet - Page 46

• Manufacturer Part Number: PIC16F630-E/SL
• Description: 14 PIN, 1.75KB STD FLASH, 64 RAM, 12 I/O,
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F630-E/SL

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F630/676
TABLE 7-1:
7.1.5
The A/D conversion is initiated by setting the
GO/DONE bit (ADCON0<1>). When the conversion is
complete, the A/D module:
• Clears the GO/DONE bit
• Sets the ADIF flag (PIR1<6>)
• Generates an interrupt (if enabled)
If the conversion must be aborted, the GO/DONE bit
can be cleared in software. The ADRESH:ADRESL
registers will not be updated with the partially complete
A/D
ADRESH:ADRESL registers will retain the value of the
FIGURE 7-2:
DS40039F-page 46
Legend: Shaded cells are outside of recommended range.
Note 1: The A/D RC source has a typical T
Operation
16 T
32 T
64 T
A/D RC
(ADFM = 0)
(ADFM = 1)
2 T
4 T
8 T
A/D Clock Source (T
2: These values violate the minimum required T
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the
OSC
OSC
OSC
OSC
OSC
OSC
conversion
conversion will be performed during Sleep.
STARTING A CONVERSION
T
ADCS2:ADCS0
AD
MSB
10-BIT A/D RESULT FORMAT
bit 7
bit 7
vs. DEVICE OPERATING FREQUENCIES
000
100
001
101
010
110
x11
sample.
Unimplemented: Read as ‘0’
AD
)
Instead,
ADRESH
2 - 6 s
100 ns
200 ns
400 ns
800 ns
20 MHz
1.6 s
3.2 s
10-bit A/D Result
AD
(1,4)
time of 4 s for V
(2)
(2)
(2)
(2)
the
MSB
AD
time.
bit 0
bit 0
2 - 6 s
12.8 s
400 ns
800 ns
previous conversion. After an aborted conversion, a
2 T
be initiated. Following the delay, an input acquisition is
automatically started on the selected channel.
7.1.6
The A/D conversion can be supplied in two formats: left
or right shifted. The ADFM bit (ADCON0<7>) controls
the output format. Figure 7-2 shows the output formats.
5 MHz
1.6 s
3.2 s
6.4 s
DD
Note:
AD
Device Frequency
> 3.0V.
(1,4)
(2)
(2)
(3)
delay is required before another acquisition can
bit 7
bit 7
The GO/DONE bit should not be set in the
same instruction that turns on the A/D.
CONVERSION OUTPUT
10-bit A/D Result
LSB
2 - 6 s
16.0 s
500 ns
1.0 s
8.0 s
4 MHz
2.0 s
4.0 s
Unimplemented: Read as ‘0’
 2010 Microchip Technology Inc.
ADRESL
(2)
(3)
(1,4)
(2)
(3)
2 - 6 s
1.25 MHz
12.8 s
25.6 s
51.2 s
1.6 s
3.2 s
6.4 s
bit 0
LSB
bit 0
(1,4)
(3)
(3)
(3)