PIC16F88-E/ML Microchip Technology, PIC16F88-E/ML Datasheet - Page 109

• Manufacturer Part Number: PIC16F88-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F88-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: SSP, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28QFN3 - SOCKET TRAN ICE 18DIP/28QFNAC164033 - ADAPTER 28QFN TO 18DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / Rohs Status: Details

FIGURE 11-7:
FIGURE 11-8:
TABLE 11-9:
 2005 Microchip Technology Inc.
0Bh, 8Bh,
10Bh,18Bh
0Ch
18h
1Ah
8Ch
98h
99h
Legend:
Note 1:
Address
Note:
RB2/SDO/RX/DT pin
Load RSR
Read
RCIF
RB2/SDO/RX/DT pin
Note:
Load RSR
Read
RCIF
x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.
INTCON
PIR1
RCSTA
RCREG
PIE1
TXSTA
SPBRG
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)
because ADDEN = 1.
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)
because ADDEN was not updated and still = 0.
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
AUSART Receive Data Register
Baud Rate Generator Register
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
SPEN
CSRC
Start
Bit 7
Start
bit
GIE
bit
—
—
bit 0
bit 0
ADIF
ADIE
PEIE
Bit 8 = 1, Address Byte
Bit 6
RX9
TX9
Bit 8 = 0, Data Byte
bit 1
bit 1
(1)
(1)
TMR0IE INT0IE
SREN
TXEN
RCIE
RCIF
Bit 5
bit 8
bit 8
CREN ADDEN
SYNC
TXIE
Bit 4
TXIF
Stop
Stop
bit
bit
SSPIF
SSPIE
RBIE
Start
Bit 3
Start
bit
—
bit
Bit 8 = 1, Address Byte
Bit 8 = 0, Data Byte
bit 0
bit 0
TMR0IF
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
BRGH
FERR
Bit 2
INT0IF
OERR
TRMT
bit 8
bit 8
Bit 1
Stop
Stop
bit
bit
Word 1
RCREG
RX9D
TX9D
Word 1
RCREG
RBIF
PIC16F87/88
Bit 0
0000 000x
-000 0000
0000 000x
0000 0000
-000 0000
0000 -010
0000 0000
POR, BOR
Value on:
DS30487C-page 107
0000 000u
-000 0000
0000 000x
0000 0000
-000 0000
0000 -010
0000 0000
Value on
all other
Resets