PIC18F4585-E/ML Microchip Technology, PIC18F4585-E/ML Datasheet - Page 3

• Manufacturer Part Number: PIC18F4585-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4585-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C, SPI, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11 bit
• Height: 0.88 mm
• Length: 8 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.2 V
• Width: 8 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4680 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / Rohs Status: Details

10. Module: Timer1/Timer3
11. Module: Timer1/Timer3
12. Module: Timer1/Timer3
© 2007 Microchip Technology Inc.
When Timer1 or Timer3 is configured for an
external clock source and the CCP1CON or
ECCP1CON register is configured with 0x0B
(Compare mode, trigger special event), the timer is
not reset on a Special Event Trigger.
Work around
Modify firmware to reset the Timer registers upon
detection of the compare match condition – TMRxL
and TMRxH.
Date Codes that pertain to this issue:
All engineering and production devices.
When the Timer1/Timer3 is in External Clock
Synchronized mode and the external clock period
is between 1 and 2 T
occasionally be skipped.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
When Timer1/Timer3 is operating in 16-bit mode
and the prescale setting is not 1:1, a write to the
TMR1H/TMR3H Buffer registers may lengthen the
duration of the period between the increments of
the timer for the period in which TMR1H/TMR3H
was written. It does not change the actual prescale
value.
Work around
Do not write to TMR1H/TMR3H while Timer1/
Timer3 is running, or else write to TMR1L/TMR3L
immediately following a write to TMR1H/TMR3H.
Do not write to TMR1H/TMR3H and then wait for
another event before also updating TMR1L/
TMR3L.
Date Codes that pertain to this issue:
All engineering and production devices.
CY
, interrupts may
PIC18F2585/2680/4585/4680
13. Module: Timer1
14. Module: MSSP
15. Module: MSSP
In 16-Bit Asynchronous Counter mode (with or
without use of the Timer1 oscillator), the TMR1H
and TMR3H buffers do not update when TMRxL is
read.
This issue only affects reading the TMRxH regis-
ters. The timers increment and set the interrupt
flags as expected. The timer registers can also be
written as expected.
Work around
1. Use 8-bit mode by clearing the RD16 bit
2. Use the internal clock synchronization option
Date Codes that pertain to this issue:
All engineering and production devices.
When the MSSP is configured for SPI Master
mode, the SDO pin cannot be disabled by setting
the TRISC<5> bit. The SDO pin always outputs
the content of SSPBUF regardless of the state of
the TRIS bit.
In Slave mode with Slave Select enabled,
SSPM3:SSPM0 = 0010 (SSPCON<3:0>), the
SDO pin can be disabled by placing a logic high
level on the SS pin (RA5).
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
After an I
register may be written for up to 10 T
additional writes are blocked. The data transfer
may be corrupted if SSPBUF is written during this
time.
The WCOL bit is set anytime an SSPBUF write
occurs during a transfer.
Work around
Avoid writing SSPBUF until the data transfer is
complete, indicated by the setting of the SSPIF bit
(PIR1<3>).
Verify the WCOL bit (SSPCON1<7>) is clear after
writing SSPBUF to ensure any potential transfer in
progress is not corrupted.
Date Codes that pertain to this issue:
All engineering and production devices.
(T1CON<7>).
by clearing the T1SYNC bit (T1CON<2>).
2
C™ transfer is initiated, the SSPBUF
DS80283E-page 3
CY
before