PIC18LF2682-I/SP Microchip Technology, PIC18LF2682-I/SP Datasheet - Page 239
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PIC18LF2682-I/SP
Manufacturer Part Number
PIC18LF2682-I/SP
Description
80KB Flash, 3KB RAM, ECAN, 1024 EEPROM 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PCM18XT0.pdf
(484 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2682-ISP.pdf
(6 pages)
4.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18LF2682-I/SP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
80KB (40K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PCM18XT0 PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2682-ISP PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- Current page: 239 of 484
- Download datasheet (9Mb)
FIGURE 18-4:
FIGURE 18-5:
TABLE 18-5:
© 2009 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
TXREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1:
Note:
(Interrupt Reg. Flag)
Reg. Empty Flag)
Reg. Empty Flag)
Write to TXREG
(Transmit Buffer
Name
Reg. Empty Flag)
(Transmit Shift
Write to TXREG
BRG Output
(Shift Clock)
(Transmit Shift
BRG Output
(Shift Clock)
TRMT bit
TXIF bit
This timing diagram shows two consecutive transmissions.
TRMT bit
Reserved in PIC18F2682/2685 devices; always maintain these bits clear.
TXIF bit
(pin)
TX
(pin)
EUSART Transmit Register
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
ABDOVF
PSPIF
PSPIE
PSPIP
TX
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
1 T
(1)
(1)
(1)
ASYNCHRONOUS TRANSMISSION
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
CY
Word 1
Transmit Shift Reg
Transmit Shift Reg.
Word 1
Word 1
Word 1
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
1 T
CY
Start bit
Start bit
Word 2
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
—
1 T
PIC18F2682/2685/4682/4685
CY
bit 0
bit 0
INT0IE
CREN
SYNC
SCKP
Bit 4
TXIF
TXIE
TXIP
bit 1
Word 1
bit 1
Word 1
ADDEN
SENDB
BRG16
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
TMR0IF
CCP1IF
CCP1IE
CCP1IP
BRGH
FERR
Bit 2
—
bit 7/8
bit 7/8
Word 2
Transmit Shift Reg.
TMR2IF
TMR2IE
TMR2IP
Stop bit
INT0IF
OERR
TRMT
WUE
Bit 1
Stop bit
Start bit
TMR1IE
TMR1IP
TMR1IF
ABDEN
RX9D
DS39761C-page 239
TX9D
RBIF
Bit 0
Word 2
on page
Values
bit 0
Reset
51
54
54
54
53
53
53
53
53
53
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