PIC18LF2682-I/SP Microchip Technology, PIC18LF2682-I/SP Datasheet - Page 412
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PIC18LF2682-I/SP
Manufacturer Part Number
PIC18LF2682-I/SP
Description
80KB Flash, 3KB RAM, ECAN, 1024 EEPROM 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PCM18XT0.pdf
(484 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2682-ISP.pdf
(6 pages)
4.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18LF2682-I/SP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
80KB (40K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PCM18XT0 PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2682-ISP PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- Current page: 412 of 484
- Download datasheet (9Mb)
literal address. For practical purposes, this means that
argument – that is, all bit-oriented and byte-oriented
PIC18F2682/2685/4682/4685
25.2.3
In addition to eight new commands in the extended set,
enabling the extended instruction set also enables
Indexed Literal Offset Addressing mode (Section 5.6.1
“Indexed Addressing with Literal Offset”). This has
a significant impact on the way that many commands of
the standard PIC18 instruction set are interpreted.
When the extended set is disabled, addresses embed-
ded in opcodes are treated as literal memory locations:
either as a location in the Access Bank (a = 0), or in a
GPR bank designated by the BSR (a = 1). When the
extended instruction set is enabled and a = 0, however,
a file register argument of 5Fh or less is interpreted as
an offset from the pointer value in FSR2 and not as a
all instructions that use the Access RAM bit as an
instructions, or almost half of the core PIC18 instructions
– may behave differently when the extended instruction
set is enabled.
When the content of FSR2 is 00h, the boundaries of the
Access RAM are essentially remapped to their original
values. This may be useful in creating backward
compatible code. If this technique is used, it may be
necessary to save the value of FSR2 and restore it
when moving back and forth between ‘C’ and assembly
routines in order to preserve the Stack Pointer. Users
must also keep in mind the syntax requirements of the
extended
“Extended Instruction Syntax with Standard PIC18
Commands”).
Although the Indexed Literal Offset Addressing mode
can be very useful for dynamic stack and pointer
manipulation, it can also be very annoying if a simple
arithmetic operation is carried out on the wrong
register. Users who are accustomed to the PIC18
programming must keep in mind that, when the
extended instruction set is enabled, register addresses
of 5Fh or less are used for Indexed Literal Offset
Addressing.
Representative examples of typical byte-oriented and
bit-oriented instructions in the Indexed Literal Offset
Addressing mode are provided on the following page to
show how execution is affected. The operand
conditions shown in the examples are applicable to all
instructions of these types.
DS39761C-page 412
Note:
BYTE-ORIENTED AND
BIT-ORIENTED INSTRUCTIONS IN
INDEXED LITERAL OFFSET MODE
Enabling
extension may cause legacy applications
to behave erratically or fail entirely.
instruction
the
set
PIC18
(see
Section 25.2.3.1
instruction
set
25.2.3.1
When the extended instruction set is enabled, the file
register argument, ‘f’, in the standard byte-oriented and
bit-oriented commands, is replaced with the literal off-
set value, ‘k’. As already noted, this occurs only when
‘f’ is less than or equal to 5Fh. When an offset value is
used, it must be indicated by square brackets (“[ ]”). As
with the extended instructions, the use of brackets indi-
cates to the compiler that the value is to be interpreted
as an index or an offset. Omitting the brackets, or using
a value greater than 5Fh within brackets, will generate
an error in the MPASM™ Assembler.
If the index argument is properly bracketed for Indexed
Literal Offset Addressing, the Access RAM argument is
never specified; it will automatically be assumed to be
‘0’. This is in contrast to standard operation (extended
instruction set disabled) when ‘a’ is set on the basis of
the target address. Declaring the Access RAM bit in
this mode will also generate an error in the MPASM
Assembler.
The destination argument, ‘d’, functions as before.
In the latest versions of the MPASM Assembler,
language support for the extended instruction set must
be explicitly invoked. This is done with either the
command line option, /y, or the PE directive in the
source listing.
25.2.4
It is important to note that the extensions to the instruc-
tion set may not be beneficial to all users. In particular,
users who are not writing code that uses a software
stack may not benefit from using the extensions to the
instruction set.
Additionally, the Indexed Literal Offset Addressing
mode may create issues with legacy applications
written to the PIC18 assembler. This is because
instructions in the legacy code may attempt to address
registers in the Access Bank below 5Fh. Since these
addresses are interpreted as literal offsets to FSR2
when the instruction set extension is enabled, the
application may read or write to the wrong data
addresses.
When porting an application to the PIC18F2682/2685/
4682/4685, it is very important to consider the type of
code. A large, re-entrant application that is written in ‘C’
and would benefit from efficient compilation will do well
when using the instruction set extensions. Legacy
applications that heavily use the Access Bank will most
likely not benefit from using the extended instruction
set.
CONSIDERATIONS WHEN
ENABLING THE EXTENDED
INSTRUCTION SET
Extended Instruction Syntax with
Standard PIC18 Commands
© 2009 Microchip Technology Inc.
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