PIC18LF2682-I/SP Microchip Technology, PIC18LF2682-I/SP Datasheet - Page 356
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18LF2682-I/SP
Manufacturer Part Number
PIC18LF2682-I/SP
Description
80KB Flash, 3KB RAM, ECAN, 1024 EEPROM 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PCM18XT0.pdf
(484 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2682-ISP.pdf
(6 pages)
4.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18LF2682-I/SP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
80KB (40K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PCM18XT0 PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2682-ISP PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- Current page: 356 of 484
- Download datasheet (9Mb)
PIC18F2682/2685/4682/4685
REGISTER 24-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER
TABLE 24-2:
DS39761C-page 356
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-1
bit 0
Note 1:
RCON
WDTCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
Name
U-0
—
This bit has no effect if the Configuration bit, WDTEN, is enabled.
Unimplemented: Read as ‘0’
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is off
IPEN
Bit 7
SUMMARY OF WATCHDOG TIMER REGISTERS
—
U-0
—
SBOREN
Bit 6
—
W = Writable bit
‘1’ = Bit is set
U-0
—
Bit 5
—
—
U-0
—
Bit 4
RI
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Bit 3
U-0
TO
—
—
Bit 2
(1)
PD
—
U-0
—
Bit 1
POR
© 2009 Microchip Technology Inc.
—
x = Bit is unknown
U-0
—
SWDTEN
Bit 0
BOR
SWDTEN
R/W-0
on page
Values
Reset
50
52
bit 0
(1)
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