ADNS-7700-HMMY Avago Technologies US Inc., ADNS-7700-HMMY Datasheet - Page 17

• Manufacturer Part Number: ADNS-7700-HMMY
• Description: USB SoC Lsr Snsr 5B+TW+OTF+KM
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-7700-HMMY

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

0x50: OTP_CTRLSTAT [0]
One-Time-Programmable (OTP) Memory
The on chip OTP memory allows device configuration flex-
ibility to override the default setting of ADNS-7700 sensors
without any external software driver. Once the OTP op-
eration is enabled, all OTP registers must be programmed
accordingly as the default values of un-program OTP reg-
isters are always zero when L2_USE_OTP register setting is
not zero value. Tips: OTP write to the OTP register can be
skipped if the setting is zero value (0x00) in order to save
the OTP programming time.
OTP address space is from 0x80 to 0xFE. OTP can be pro-
grammed via USB interface using Set Vendor Test and Get
Vendor Test commands.
Figure 16. OTP Byte Write Flow Chart
17
0x4F: OTP_CTRL [0] = 1
0x4F: OTP_CTRL [0]
Yes
No
Write OTP program bit
Read OTP program bit
Write OTP enable bit
Write OTP addr byte
Write OTP data byte
Read OTP status bit
OTP write pass
More bytes?
Repeat = 1
bit = 0?
bit = 1?
Done
Start
Yes
Yes
No
No
Repeat = repeat + 1
Repeat = 10?
OTP write fail
Bad chip
OTP Byte Write Operation
OTP write operation flow chart is shown in Figure 16.
1. Set OTP enable bit in OTP_CONFIG register, 0x4C:
2. Write the OTP register address byte to OTP_ADDR
3. Write the OTP data byte to OTP_DATA register, 0x4E.
4. Set write enable bit in OTP_CTRL register, 0x4F to
5. Read the write enable bit status in OTP_CTRL register,
6. Read the write status bit in OTP_CTRLSTAT register,
7. If Step 6b is repeated up to 10 times, OTP write operation
Yes
No
0x4C: OTP_CONFIG [0] = 1
0x4D: OTP_ADDR [7:0]
0x4E: OTP_DATA [7:0]
OTP_EN = 1.
register, 0x4D.
enable write command to OTP: WR = 1.
0x4F. If WR = 1, repeat reading the bit status until it is
clear.
0x50.
a. If WR_OK = 1, OTP write operation is completed.
b. If WR_OK = 0, repeat Step 4.
is failed and the chip is confirmed as defective unit.
Repeat Step 2 for more OTP byte write operations.