ADNS-7700-HMMY Avago Technologies US Inc., ADNS-7700-HMMY Datasheet - Page 19

• Manufacturer Part Number: ADNS-7700-HMMY
• Description: USB SoC Lsr Snsr 5B+TW+OTF+KM
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-7700-HMMY

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

OTP Lock Operation
OTP lock operation MUST be performed once OTP write to
OTPLOCK2 register for the sensor to function. DO not reset
or power up the chip right after OTP write to OTPLOCK2
register, otherwise the chip will be malfunction. The OTP
lock operation flow chart is shown in Figure 18.
1. After OTP write to OTPLOCK2 register, set OTP enable
2. Set OTP lock bit in OTP_CTRL register, 0x4F to enable
Figure 18. OTP Byte Lock Flow Chart
19
Repeat = repeat + 1
bit in OTP_CONFIG register, 0x4C: OTP_EN = 1.
OTP lock command: LOCK_L2 = 1.
Repeat = 10?
OTP lock fail
Bad chip
Yes
No
No
Write OTP enable bit
OTPLOCK2 register,
Read lock status bit
Read CRC status bit
OTP Write 0xFF to
Write OTP lock bit
Read OTP lock bit
lock & crc = 1?
Repeat = 1
OTP locked
bit = 0?
0xFA
Done
Yes
Yes
No
0x4C: OTP_CONFIG [0] = 1
0x4F: OTP_CTRL [2] = 1
0x4F: OTP_CTRL [2]
0x50: OTP_CTRLSTAT [2]
0x50: OTP_CTRLSTAT [3]
3. Read the OTP lock bit status in OTP_CTRL register, 0x4F. If
4. Read the lock status and CRC bits in OTP_CTRLSTAT
5. If Step 4b is repeated up to 10 times, OTP lock operation
LOCK_L2 = 1, repeat reading the bit status until it is clear.
register, 0x50.
a. If both L2_LOCK_OK and L2_CRC_OK = 1, OTP lock
b. If either L2_LOCK_OK or L2_CRC_OK = 0, repeat Step
is failed and the chip is confirmed as defective unit.
operation is completed.
2 until both bits are set.