AFBR-703SDDZ Avago Technologies US Inc., AFBR-703SDDZ Datasheet - Page 19
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AFBR-703SDDZ
Manufacturer Part Number
AFBR-703SDDZ
Description
SFP+ 850nm 1/10GbE SR MMF,Gen2 STD
Manufacturer
Avago Technologies US Inc.
Series
-r
Datasheet
1.AFBR-703SDDZ.pdf
(22 pages)
Specifications of AFBR-703SDDZ
Data Rate
10.312Gbd
Wavelength
850nm
Applications
Ethernet
Voltage - Supply
3.135 V ~ 3.465 V
Connector Type
LC Duplex
Mounting Type
SFP+
Optical Fiber Type
TX/RX
Data Transfer Rate
10313MBd
Optical Rise Time
0.028ns
Optical Fall Time
0.028ns
Operating Temperature Classification
Commercial
Peak Wavelength
860nm
Package Type
SFP
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Output Current
20mA
Operating Temp Range
0C to 70C
Mounting
Snap Fit To Panel
Pin Count
20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 16. EEPROM Serial ID Memory Contents - Extended Control/Status (Address A2h, Byte 118)
Notes:
1. The response time for soft commands of the AFBR-703SDDZ is 100ms as specified by SFF-8472.
Table 17. EEPROM Serial ID Memory Contents – Soft Commands (Address A2h, Byte 110)
Bit #
7
6
5
4
3
2
1
0
Notes:
1. The response time for soft commands of the AFBR-703SDDZ is 100 msec as specified by SFF-8472.
2. Bit 6 is logic OR’d with the SFP TX_DISABLE input on contact 3; either asserted will disable the SFP+ transmitter.
19
Bit #
7
6
5
4
3
2
1
0
Status/
Control Name
TX_ DISABLE State
Soft TX_ DISABLE
Reserved
Reserved
Soft RS0 Select
TX_FAULT State
RX_LOS State
Data Ready (Bar)
Status/
Control Name
Reserved
Reserved
Reserved
Reserved
Soft RS1 Select
Reserved
Class2 Operation State
Power Class Select
Description
Digital state of SFP TX_ DISABLE Input (1 = TX_DISABLE asserted)
Read/write bit for changing digital state of TX_DISABLE function
Read/write bit that allows software RX rate control.
Writing ‘1’ selects full speed RX operation. Power on default is logic zero/low.
This bit is OR’d with the hardware RS0 pin value (see Appendix).
Digital state of the SFP TX_FAULT Output (1 = TX_FAULT asserted)
Digital state of the SFP RX_LOS Output (1 = RX_LOS asserted)
Indicates transceiver is powered and real time sense data is ready. (0 = Ready)
Description
Read/write bit that allows software Tx rate control. Writing '1' selects full lspeed
Tx operation. Power on default is logic zero/low. This bit is OR'd with the hard-
ware RS1 pin value (see Appendix).
Value=0. Power class2 operation is not active.
Has no effect.
Notes
Note 1
Note 1, 2
Note 1
Note 1
Notes
1