AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 34

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9548
draining, the water level in the tub eventually rises above the
high water mark (+1024), which causes the phase lock detector
to indicate lock. If more draining is taking place than filling,
then the water level in the tub eventually falls below the low
water mark (−1024), which causes the phase lock detector to
indicate unlock. The ability to specify the threshold level, fill
rate, and drain rate enables the user to tailor the operation of
the phase lock detector to the statistics of the timing jitter
associated with the input reference signal.
Note that whenever the AD9548 enters the free-run or holdover
mode, the DPLL phase lock detector indicates unlocked. In
addition, whenever the AD9548 performs a reference switch-
over, the state of the lock detector prior to the switch is
preserved during the transition period.
DPLL Frequency Lock Detector
The operation of the frequency lock detector is identical to that
of the phase lock detector. The only difference is that the fill or
drain decision is based on the period deviation between the
reference and feedback signals of the DPLL instead of the phase
error at the output of the PFD.
The frequency lock detector uses a 24-bit frequency threshold
register specified in units of picoseconds. Thus, the frequency
threshold value extends from 0 μs to ±16.777215 μs. It represents
the magnitude of the difference in period between the reference
and feedback signals at the input to the DPLL. For example, if
the reference signal is 1.25 MHz and the feedback signal is 1.38
MHz, then the period difference is approximately 75.36 ns
(|1/1,250,000 − 1/1,380,000| ≈ 75.36 ns).
2048
1024
–1024
0
–2048
PREVIOUS
STATE
Figure 41. Lock Detector Diagram
FILL
RATE
TUNING WORD
FREQUENCY
DRAIN
RATE
LOCKED
(FTW)
48
48-BIT ACCUMULATOR
UNLOCKED
48
UNLOCK LEVEL
48
D
LOCK LEVEL
Q
Figure 42. DDS Block Diagram
Rev. A | Page 34 of 112
19
OFFSET
PHASE
16
19
DIRECT DIGITAL SYNTHESIZER
DDS Overview
One of the primary building blocks of the digital PLL is a direct
digital synthesizer (DDS). The DDS behaves like a sinusoidal
signal generator. The frequency of the sinusoid generated by the
DDS is determined by a frequency tuning word (FTW), which
is a digital (that is, numeric) value. Unlike an analog sinusoidal
generator, a DDS uses digital building blocks and operates as a
sampled system. Thus, it requires a sampling clock (f
serves as the fundamental timing source of the DDS. The
accumulator behaves as a modulo-2
programmable step size (FTW). A block diagram of the DDS
appears in Figure 42.
The input to the DDS is the 48-bit FTW. The FTW serves as a
step size value. On each cycle of f
value of the FTW to the running total at its output. For
example, given FTW = 5, the accumulator counts by fives,
incrementing on each f
reaches the upper end of its capacity (2
point, it rolls over but retains the excess. The average rate at
which the accumulator rolls over establishes the frequency of
the output sinusoid. The average rollover rate of the accumulator
establishes the output frequency (f
Solving this equation for FTW yields
For example, given that f
FTW = 437,749,988,378,041 (0x27D028A1DFB9).
Note that the minimum DAC output frequency is 62.5 MHz;
therefore, normal operation requires an FTW that yields an
output frequency in excess of this lower bound.
CONVERSION
AMPLITUDE
ANGLE TO
FTW
f
DDS
⎛
⎜
⎝
round
FTW
2
14
48
⎡
⎢
⎢
⎣
⎞
⎟
⎠
2
f
48
S
S
(14-BIT)
⎛
⎜
⎜
⎝
cycle. Over time, the accumulator
DAC
S
f
= 1 GHz and f
DDS
f
S
⎞
⎟
⎟
⎠
f
S
⎤
⎥
⎥
⎦
S
DDS
, the accumulator adds the
48
) of the DDS and is given by
DAC+
DAC–
counter with a
48
DDS
in this case), at which
= 155.52 MHz, then
S
) that