AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 55

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I²C SERIAL PORT OPERATION
The I
control pins and is a de facto standard throughout the I
industry. However, its disadvantage is programming speed, which
is 400 kbps maximum. The AD9548 I2C port design is based on
the I2C fast mode standard from Philips, so it supports both the 100
kHz standard mode and 400 kHz fast mode. Fast mode imposes a
glitch tolerance requirement on the control signals. That is, the
input receivers ignore pulses of less than 50 ns duration.
The AD9548 I2C port consists of a serial data line (SDA) and a
serial clock line (SCL). In an I2C bus system, the AD9548 is
connected to the serial bus (data bus SDA and clock bus SCL)
as a slave device; that is, no clock is generated by the AD9548.
The AD9548 uses direct 16-bit memory addressing instead of
traditional 8-bit memory addressing.
The AD9548 allows up to seven unique slave devices to occupy
the I
transmitted as part of an I
matching slave address responds to subsequent I
The device slave address is 1001xxx (the three right bits are
determined by the M0 to M2 pins). The four MSBs (1001) are
hard-wired, while the three LSBs (xxx, determined by the M0 to
M2 pins) are programmable via the power-up state of the
multifunction pins (see the Initial Pin Programming section).
I
A summary of the various I
2
C Bus Characteristics
2
C bus. These are accessed via a 7-bit slave address
2
C interface has the advantage of requiring only two
SDA
SCL
S
SDA
SCL
2
MSB
C packet. Only the device with a
2
1
C protocols appears in Table 33.
START CONDITION
S
2
3 TO 7
2
C commands.
2
Figure 60. Start and Stop Conditions
C
8
Figure 61. Acknowledge Bit
SLAVE-RECEIVER
Rev. A | Page 55 of 112
ACK FROM
9
Table 33. I
Abbreviation
S
Sr
P
A
A
W
R
The transfer of data is shown in Figure 59. One clock pulse is
generated for each data bit transferred. The data on the SDA
line must be stable during the high period of the clock. The
high or low state of the data line can only change when the
clock signal on the SCL line is low.
SDA
SCL
Start/stop functionality is shown in Figure 60. The start condition
is characterized by a high-to-low transition on the SDA line
while SCL is high. The start condition is always generated by
the master to initialize a data transfer. The stop condition is
characterized by a low-to-high transition on the SDA line while
SCL is high. The stop condition is always generated by the
master to terminate a data transfer. Every byte on the SDA line
must be eight bits long. Each byte must be followed by an
acknowledge bit; bytes are sent MSB first.
1
2
2
C Bus Abbreviation Definitions
DATA VALID
DATA LINE
STABLE;
3 TO 7
Figure 59. Valid Bit Transfer
STOP CONDITION
P
Definition
Start
Repeated start
Stop
Acknowledge
Nonacknowledge
Write
Read
8
ALLOWED
CHANGE
OF DATA
SLAVE-RECEIVER
ACK FROM
9
10
P
AD9548