AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 75

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DPLL CONFIGURATION (REGISTER 0300 TO REGISTER 031B)
Table 56. Free Running Frequency Tuning Word
Address
0300
0301
0302
0303
0304
0305
1
Table 57. Update TW
Address
0306
Table 58. Pull-In Range Lower Limit
Address
0307
0308
0309
030A
030B
030C
1
Table 59. DDS Phase Offset
Address
030D
030E
1
Table 60. Fixed Closed-Loop Phase Lock Offset
Address
030F
0310
0311
0312
0313
1
The default free running tuning word is 0x000000 = 0, which equates to 0 Hz.
The default pull-in range lower limit is 0 and the upper range limit is 0xFFFFFF, which effectively spans the full output frequency range of the DDS.
The default DDS phase offset is 0.
The default fixed closed loop phase lock offset is 0.
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:1]
[0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bits
Bits
Bits
[7:0]
Bits
[7:0]
[7:0]
Bits
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
1
Bit Name
Frequency
(expressed as a 48-bit
frequency tuning
word)
Unused
Update TW
Bit Name
Bit Name
Pull-in range lower
limit (expressed as a
24-bit frequency
tuning word)
Pull-in range upper
limit (expressed as a
24-bit frequency
tuning word)
Bit Name
Open-loop phase
offset (expressed in
π/2
Bit Name
Fixed phase lock
offset (expressed in
pico-seconds)
15
radians)
1
1
1
Description
A Logic 1 written to this bit transfers the free running frequency tuning word
(Register 0300 to Register 0305) to the register imbedded in the tuning word
processing logic. Note that it is not necessary to write the update TW bit when the
device is in free-run mode. This is an autoclearing bit.
Description
Lower limit pull-in range, Bits[7:0]
Lower limit pull-in range, Bits[15:8]
Lower limit pull-in range, Bits[23:9]
Upper limit pull-in range, Bits[7:0]
Upper limit pull-in range, Bits[15:8]
Upper limit pull-in range, Bits[23:9]
Description
DDS phase offset, Bits[7:0]
DDS phase offset, Bits[15:8]
Description
Fixed phase lock offset, Bits[7:0]
Fixed phase lock offset, Bits[15:8]
Fixed phase lock offset, Bits[23:16]
Fixed phase lock offset, Bits[31:24]
Fixed phase lock offset, Bits[39:32]
Description
Free running frequency tuning word, Bits[7:0]
Free running frequency tuning word, Bits[15:8]
Free running frequency tuning word, Bits[23:9]
Free running frequency tuning word, Bits[31:24]
Free running frequency tuning word, Bits[39:32]
Free running frequency tuning word, Bits[47:40]
Rev. A | Page 75 of 112
AD9548