AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 66

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9548
Addr
06C0
06C1
06C2
06C3
06C4
06C5
06C6
06C7
06C8
06C9
06CA
06CB
06CC
06CD
06CE
06CF
06D0
06D1
06D2
06D3
06D4
06D5
06D6
06D7
06D8
06D9
06DA
06DB
06DC
06DD
06DE
06DF
06E0
06E1
06E2
06E3
06E4-
06FF
0700-
07FF
0A00
0A01
0A02
Opt
S
C
S
Name
Validation
Redetect
timeout
Digital loop
filter
coefficients
Frequency
multiplica-
tion
Lock
detectors
Profile 4
through
Profile 7
General
power-down
Loop
mode
Cal/sync
D7
Validation timer (milliseconds) [15:0] (up to 65.5 sec)
Redetect timer (milliseconds) [15:0] (up to 65.5 sec)
Alpha-0 linear [15:0]
Alpha-2 exponent [1:0]
Beta-0 linear [6:0]
Beta-0 linear [14:7]
Unused
Gamma-0 linear [15:0]
Unused
Delta-0 linear [7:0]
Delta-1
exponent
[0]
Alpha-3 exponent [3:0]
R [23:0]
Unused
S [23:0]
Unused
V [7:0]
U [3:0]
Unused
Phase lock threshold (picoseconds) [15:0]
Phase lock fill rate [7:0]
Phase lock drain rate [7:0]
Frequency lock threshold (picoseconds) [23:0]
Frequency lock fill rate [7:0]
Frequency lock drain rate [7:0]
Unused
The functionality of the Profile 4 through Profile 7 address locations (Address 0700 to Address 07FF) is identical
to that of the Profile 0 through Profile 3 address locations (Address 0600 to Address 06FF).
Reset Sans
regmap
Unused
Unused
Beta-1 exponent [4:0]
Delta-0 linear [14:8]
D6
Unused
User
holdover
D5
Alpha-1 exponent [5:0]
Gamma-1 exponent [4:0]
R [29:24]
S [29:24]
U [9:4]
SYSCLK
power-
down
User
freerun
Rev. A | Page 66 of 112
D4
Reference
power-
down
User selection mode [1:0]
Profile 4 through Profile 7
Operational controls
Delta-1 exponent [4:1]
Unused
D3
TDC
power-
down
D2
DAC
power-
down
User reference selection [2:0]
D1
Beta-0
linear
[16:15]
V [9:8]
Dist
power-
down
Sync
distribu-
tion
D0
Alpha-2
exponent
[2]
00
Gamma-0
linear [16]
Full
power-
down
Calibrate
system
clock
Def
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00