CDB4228A Cirrus Logic Inc, CDB4228A Datasheet - Page 6

• Manufacturer Part Number: CDB4228A
• Description: Development Kit
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4228A

• Silicon Manufacturer: Cirrus Logic
• Application Sub Type: Codec
• Kit Application Type: Audio / Video / TV
• Silicon Core Number: CS4228A
• Features: PC Software Provides Easy To Use Board & Device Control
• Kit Contents: Evaluation Board
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7.1
The SMODE[4..0] switches on S5 set the serial
mode and the LRCLK/SCLK direction of all other
devices in the system except the CS4228A. The de-
vices controlled by SMODE include the CS8414,
the CS8404, and the DAP. SMODE settings on S5
are only active when in EXTRNL mode. The
SMODE mapping is shown in Table 1. Care must
be taken when setting up SMODE so that the LR-
CLK/SCLK direction corresponds with the
CS4228A master/slave setting to avoid bus conten-
tion. The CS4228A serial port master/slave mode is
set in the Serial Port Mode register 0x0D.
7.2
The board level MCLK source is controlled by the
MCLK-SEL[2..0] switches on S5 when in EX-
TRNL mode. The multiplexer settings are shown in
Table 3. The MCLK source should be the CS8414
whenever the S/PDIF data source is used.
7.3
The TX_MCLK[1..0] switches on S5 control the
clock divider for the CS8404 S/PDIF transmitter
when in EXTRNL mode. The transmitter must be
supplied a 128 Fs MCLK which is sourced from the
6
Serial Mode
MCLK Multiplexer
Transmitter Clock Divider
SMODE
10 - 31
[4..0]
0
1
2
3
4
5
6
7
8
9
Board Level Serial Mode
I2S, TX Master, 64Fs SCLK only
I2S, CODEC Master
I2S, DAP Master
Right Justified, TX Master, 16 bits
Right Justified, CODEC master
Right Justified, DAP master
Left Justified, CODEC master
Left Justified, DAP master
Left Justified, test mode
Left Justified, test mode
I2S, CODEC master
Table 1. Board Level Serial Mode Settings
CS8414
MODE
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
CS4228A MCLK multiplexer. The clock divider
ratios are shown in Table 5.
8. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by four
binding posts (+5V, GND, +12V, -12V). The +5V
input supplies power to the analog and digital +5
Volt circuitry and to a 3.3V voltage regulator.
There is a power supply header for selecting either
5V or 3.3V supplies to the CS4228A VL pin. A
second header selects the interface voltage for the
programmable logic device that supplies the con-
trol port interface. The VL setting should always be
equal or greater than the PLD PWR to prevent
noise due to charge injection.
9. GROUNDING AND POWER SUPPLY
The CS4228A requires careful attention to power
supply and grounding arrangements to optimize
performance. The decoupling capacitors are locat-
ed as close to the CS4228A as possible. Extensive
use of ground plane fill on both the analog and dig-
ital sections of the evaluation board yields large re-
ductions in radiated noise.
DECOUPLING
CS8404
MODE
Output
Input
Input
Input
Input
Input
Input
OFF
OFF
OFF
OFF
DAP CLK
MODE
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
CS8414
M[3..0]
15
15
15
15
2
3
3
5
0
1
3
CDB4228A
DS511DB1
CS8404
M[2..0]
4
4
4
5
4
1
1
1
0
4
4