CDB4228A Cirrus Logic Inc, CDB4228A Datasheet - Page 9

• Manufacturer Part Number: CDB4228A
• Description: Development Kit
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4228A

• Silicon Manufacturer: Cirrus Logic
• Application Sub Type: Codec
• Kit Application Type: Audio / Video / TV
• Silicon Core Number: CS4228A
• Features: PC Software Provides Easy To Use Board & Device Control
• Kit Contents: Evaluation Board
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

J3
TERMINAL BLUE
+12V
J4
TERMINAL BLACK
GND
J5
TERMINAL GREEN
-12V
J6
TERMINAL RED
+5V
PHONO JACK RA
PHONO JACK RA
GND
GND
J1
J2
1
1
1
1
1
1
VCC
VD
VCC
VD
+3.3V
+3.3V
+5V
+5V
VLOGIC SEL
JP11
HEADER 2X2
VD SEL
1
3
JP6
HEADER 2X2
1
3
A/D Input
A/D Input
2
4
2
4
AINL
AINR
+12VBUS
GND
-12VBUS
+5VBUS
VL
OUTL+
OUTR+
OUTR-
OUTL-
R5
R6
R7
Power
Power
+12VBUS
GND
-12VBUS
+5VBUS
PPRESETn
AINL-
AINL+
AINR-
AINR+
TP16
TP18
TP20
10k
3.16k
10k
X_RESETn
PPRESETn
Host Interface
Parallel Port
MRESETn
MUTEC
RESETn
MUTE
PPRESETn
X_RESETn
MRESETn
MUTEC
MUTE
STATUS[3..0]
C9
47nf
TP3
TP5
TP7
TP9
TP11
TP12
TP14
STROBEn
SCL
SDA/CDIN
AD0/CS
D[7..0]
A[1..0]
ACKn
GND
+
SPDIF Out
SPDIF TX
CLKIN
SCLK
LRCLK
SDIN1
SDIN2
SDIN3
SDOUT
C7
10uf
R98
R99
R100
R101
R102
R103
D[7..0]
A[1..0]
STROBEn
STATUS[3..0]
ACKn
Figure 1. CDB4228A Top Level Schematic
TP23
TP25
C13
47nf
RESETn
TX_CBL
LRCLK
M[2..0]
TX_CBL
TX_C
TX_U
RX_CBL
RX_C
RX_U
RXPWR
RX_VERF
RX_ERF
MRESETn
SCLK
TP26
MCLK
TX_U
TX_C
SDIN
MRESETn
MUTEC
150
150
150
150
150
150
TX_MCLK
SCLK
LRCLK
SDOUT
TX_M[2..0]
MRESETn
TX_U
TX_C
TX_CBL
Programmable Logic
PLD
A[1..0]
ACKn
TX_C
TX_U
RX_C
RX_VERF
MRESETn
D[7..0]
STROBEn
STATUS[3..0]
TX_CBL
RX_CBL
RX_U
RXPWR
RX_ERF
10
11
12
13
14
15
5
6
3
2
1
4
9
8
7
U3
CS4228A-KS
CLKIN
SCLK
LRCLK
SDIN1
SDIN2
SDIN3
SDOUT
SCL/CCLK
SDA/CDIN
AD0/CS
RESET
MUTEC
VL
VD
DGND
REFCLK_CTRL[3..0]
MODE_CTRL[9..0]
DAP_SDIN[3..1]
SPDIF_SDOUT
CTRL_MODE
SDA/CDOUT
SDIN_CTRL
TX_M[2..0]
DAP_CTRL
SDIN[3..1]
RX_M[3..0]
AOUT1
AOUT2
AOUT3
AOUT4
AOUT5
AOUT6
SPDIF In
SPDIF RX
AINR+
AINL+
AGND
TX_MCLK
AINR-
AINL-
X_CTRL
AD0/CS
FILT
LRCLK
CLKIN
VA
CDIN
SCLK
SCL
16
17
20
19
18
23
24
25
26
27
28
21
22
RX_VERF
SCL
SDA/CDIN
MUTEC
AD0/CS
SCLK
LRCLK
SDIN[3..1]
DAP_SDIN[3..1]
SPDIF_SDOUT
SDIN_CTRL
TX_M[2..0]
RX_M[3..0]
DAP_CTRL
REFCLK_CTRL[3..0]
X_CTRL
CTRL_MODE
CLKIN
TX_MCLK
MODE_CTRL[9..0]
RX_CBL
RX_ERF
RXPWR
SDOUT
FSYNC
AINR+
AINR-
AINL+
AINL-
FILT
AOUT1
AOUT2
AOUT3
AOUT4
AOUT5
AOUT6
MCLK
SCLK
M[3..0]
RX_U
RX_C
TP27
GND
SPDIF_MCLK
SCLK
LRCLK
SPDIF_SDOUT
RX_M[3..0]
RXPWR
RX_C
RX_U
RX_CBL
RX_ERF
RX_VERF
C12
47nf
TP4
TP6
TP8
TP10
TP15
TP17
TP19
TP21
TP22
TP24
+
C8
10uf
SDIN1
SDIN2
SDIN3
GND
VA
+
C5
10uf
GND
SPDIF_SDOUT
DAP_SDIN1
SPDIF_SDOUT
DAP_SDIN2
SPDIF_SDOUT
DAP_SDIN3
C6
47nf
TP13
JP3
HEADER 2X2
JP4
HEADER 2X2
JP5
HEADER 2X2
1
3
1
3
1
3
2
4
2
4
2
4
SPDIF_MCLK
DAP_MCLK
REFCLK_CTRL[3..0]
X_CTRL
SDIN_CTRL
CTRL_MODE
SDOUT
MODE_CTRL[9..0]
DAP_MCLK
SCLK
LRCLK
SDOUT
DAP_CTRL
SDIN1
SDIN2
SDIN3
Digital Audio Port (DAP)/External Control
DAP
Control Switches
CONTROL
Reference Clock
RefClk
LRCLK
MCLK
SCLK
DAP_SDOUT
DAP_CTRL
X_CTRL
SDIN_CTRL
SDOUT_LOAD
MODE_CTRL[9..0]
DAP_MCLK
REFCLK_CTRL[3..0]
CTRL_MODE
SPDIF_MCLK
AOUT1
AOUT2
AOUT3
AOUT4
AOUT5
AOUT6
MUTE
DAP_SDIN[3..1]
X_AD0/CS
X_RESETn
Output Buffer1
Out1
Output Buffer2
Out2
Output Buffer3
Out3
Output Buffer4
Out4
Output Buffer5
Out5
Output Buffer6
Out6
X_SDA
MUTEC
X_SCL
MUTE
MUTE
MUTE
MUTE
IN
MUTE
IN
IN
IN
IN
MUTE
IN
REFCLK
DAP_SDIN[3..1]
SDA/CDIN
SCL
AD0/CS
X_RESETn
MUTEC
CLKIN
GND
R104
75