IP-AGX-PCIE/1 Altera, IP-AGX-PCIE/1 Datasheet - Page 317
![IP CORE - X1 Lane PCI Express For Arria GX](/photos/24/19/241936/4696145_sml.jpg)
IP-AGX-PCIE/1
Manufacturer Part Number
IP-AGX-PCIE/1
Description
IP CORE - X1 Lane PCI Express For Arria GX
Manufacturer
Altera
Datasheet
1.IP-AGX-PCIE1.pdf
(362 pages)
Specifications of IP-AGX-PCIE/1
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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Chapter :
Descriptor/Data Interface
Figure B–9. RX Transaction with a Data Payload and Wait States Waveform
Table B–5. RX Minimum and Maximum Latency Values in Clock Cycles Between Receive Signals
December 2010 Altera Corporation
rx_req
rx_req
rx_req
rx_retry
Descriptor
Signals
Signal 1
Data
Signals
rx_desc[135:128]
rx_ack
rx_dfr
rx_dv
rx_req
rx_desc[127:64]
Signal 2
rx_data[63:32]
rx_desc[63:0]
rx_data[31:0]
■
rx_be[7:0]
Dependencies Between Receive Signals
Table B–5
between various receive signals.
rx_mask
rx_abort
rx_retry
rx_ack
The application layer deasserts rx_ws at clock cycle 11, thereby ending an
application interface-induced wait state.
rx_req
rx_ws
rx_dfr
rx_dv
Min
1
0
1
1
clk
describes the minimum and maximum latency values in clock cycles
1
Typical
1-2
1
0
2
2
CPLD 4 DW
Max
N
0
N
N
3
valid
valid
Always asserted on the same clock cycle if a data payload is present,
except when a previous data transfer is still in progress. Refer to
Figure B–8 on page
Assuming data is sent.
rx_req refers to the next transaction request.
4
5
DW 0
0xF0
6
B–10.
DW 2
DW 1
0xFF
7
Notes
8
—
9
PCI Express Compiler User Guide
DW 3
0x0F
11
B–11
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