IP-AGX-PCIE/1 Altera, IP-AGX-PCIE/1 Datasheet - Page 331
![IP CORE - X1 Lane PCI Express For Arria GX](/photos/24/19/241936/4696145_sml.jpg)
IP-AGX-PCIE/1
Manufacturer Part Number
IP-AGX-PCIE/1
Description
IP CORE - X1 Lane PCI Express For Arria GX
Manufacturer
Altera
Datasheet
1.IP-AGX-PCIE1.pdf
(362 pages)
Specifications of IP-AGX-PCIE/1
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
- Current page: 331 of 362
- Download datasheet (7Mb)
Chapter :
Descriptor/Data Interface
Table B–11. Completion Interface Signals
December 2010 Altera Corporation
cpl_err[2:0]
cpl_pending
Completion Interface Signals for Descriptor/Data Interface
Signal
Table B–11
descriptor/data interface.
I/O
describes the signals that comprise the completion interface for the
I
I
Completion error. This signal reports completion errors to the configuration space
by pulsing for one cycle. The three types of errors that the application layer must
report are:
■
■
■
For ×1 and ×4 the wrapper output is a 7-bit signal with the following format:
{3’h0, cpl_err[2:0], 1’b0}
Completion pending. The application layer must assert this signal when a master
block is waiting for completion, for example, when a transaction is pending. If this
signal is asserted and low power mode is requested, the IP core waits for the
deassertion of this signal before transitioning into low-power state.
cpl_err[0]: Completion timeout error. This signal must be asserted when a
master-like interface has performed a non-posted request that never receives a
corresponding completion transaction after the 50 ms time-out period. The IP
core automatically generates an error message that is sent to the root complex.
cpl_err[1]: Completer abort error. This signal must be asserted when a
target block cannot process a non-posted request. In this case, the target block
generates and sends a completion packet with completer abort (CA) status to
the requestor and then asserts this error signal to the IP core. The block
automatically generates the error message and sends it to the root complex.
cpl_err[2]: Unexpected completion error. This signal must be asserted when
a master block detects an unexpected completion transaction, for example, if
no completion resource is waiting for a specific packet.
Description
PCI Express Compiler User Guide
B–25
Related parts for IP-AGX-PCIE/1
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![IP-AGX-PCIE/4](/photos/24/19/241936/4696145_tmb.jpg)
Part Number:
Description:
IP CORE - PCI Express X1 And X4 Lanes For Arria GX
Manufacturer:
Altera
Datasheet:
![DK-CYCII-2C20N](/photos/9/20/92074/mfgdk-cycii-2c20nboard_tmb.jpg)
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610IPC-25](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-30](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-12](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10A](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![P85C224-66](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP320PC](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP2A15B724C7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet: