IP-AGX-PCIE/1 Altera, IP-AGX-PCIE/1 Datasheet - Page 324
IP-AGX-PCIE/1
Manufacturer Part Number
IP-AGX-PCIE/1
Description
IP CORE - X1 Lane PCI Express For Arria GX
Manufacturer
Altera
Datasheet
1.IP-AGX-PCIE1.pdf
(362 pages)
Specifications of IP-AGX-PCIE/1
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
- Current page: 324 of 362
- Download datasheet (7Mb)
B–18
Figure B–13. TX Transfer for A Single DWORD Write
Figure B–14. TX State Machine Is Busy with the Preceding Transaction Layer Packet Waveform
PCI Express Compiler User Guide
Descriptor
Data
Signals
Signals
Descriptor
Signals
Data
Signals
tx_desc[127:0]
tx_data[63:32]
tx_data[31:0]
Figure B–13
Transaction Layer Not Ready to Accept Packet
In this example, the application transmits a 64-bit memory read transaction of six
DWORDs. Address bit 2 is set to 0. Refer to
Data transmission cannot begin if the IP core’s transaction layer state machine is still
busy transmitting the previous packet, as is the case in this example.
tx_ack
tx_req
tx_dfr
tx_ws
tx_err
tx_dv
clk
tx_desc[127:0]
tx_data[63:32]
tx_data[31:0]
1
shows the IP core transmitting a memory write of one DWORD.
tx_ack
tx_req
tx_ws
tx_err
tx_dfr
tx_dv
2
clk
1
3
MEMWR32
2
4
DW0
3
MEMWR64
5
Figure
4
B–14.
6
5
December 2010 Altera Corporation
7
6
7
Descriptor/Data Interface
8
9
Chapter :
Related parts for IP-AGX-PCIE/1
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
IP CORE - PCI Express X1 And X4 Lanes For Arria GX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet: